Merge branch 'docs-next' of git://git.lwn.net/linux-2.6

[pandora-kernel.git] / arch / sh / kernel / cpu / sh4a / clock-sh7723.c

diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index b433185..d3938f0 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -38,8 +38,6 @@
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-       .name           = "rclk",
-       .id             = -1,
        .rate           = 32768,
 };
 
@@ -48,8 +46,6 @@ static struct clk r_clk = {
  * from the platform code.
  */
 struct clk extal_clk = {
-       .name           = "extal",
-       .id             = -1,
        .rate           = 33333333,
 };
 
@@ -71,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
 };
 
 static struct clk dll_clk = {
-       .name           = "dll_clk",
-       .id             = -1,
        .ops            = &dll_clk_ops,
        .parent         = &r_clk,
        .flags          = CLK_ENABLE_ON_INIT,
@@ -96,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-       .name           = "pll_clk",
-       .id             = -1,
        .ops            = &pll_clk_ops,
        .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -125,32 +117,34 @@ static struct clk_div4_table div4_table = {
 
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-       [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
-       [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
-       [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
-       [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
-       [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
-       [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
+       [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
+       [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
+       [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
+       [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
+       [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
+       [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
 };
 
 enum { DIV4_IRDA, DIV4_ENABLE_NR };
 
 struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
-       [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
+       [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
 };
 
 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
 
 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
-       [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
-       [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
+       [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
+       [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
 };
-struct clk div6_clks[] = {
-       SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+enum { DIV6_V, DIV6_NR };
+
+struct clk div6_clks[DIV6_NR] = {
+       [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
 };
 
 static struct clk mstp_clks[] = {
@@ -209,6 +203,26 @@ static struct clk mstp_clks[] = {
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 
 static struct clk_lookup lookups[] = {
+       /* main clocks */
+       CLKDEV_CON_ID("rclk", &r_clk),
+       CLKDEV_CON_ID("extal", &extal_clk),
+       CLKDEV_CON_ID("dll_clk", &dll_clk),
+       CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+       /* DIV4 clocks */
+       CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+       CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+       CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+       CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+       CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
+       CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+       CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
+       CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
+       CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
+
+       /* DIV6 clocks */
+       CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+
        /* MSTP clocks */
        CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
        CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
@@ -341,7 +355,7 @@ int __init arch_clk_init(void)
                                        DIV4_REPARENT_NR, &div4_table);
 
        if (!ret)
-               ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+               ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
        if (!ret)
                ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);