#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
+#include <asm/clkdev.h>
#include <asm/clock.h>
#include <asm/hwblk.h>
#include <cpu/sh7722.h>
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
- .name = "rclk",
- .id = -1,
.rate = 32768,
};
* from the platform code.
*/
struct clk extal_clk = {
- .name = "extal",
- .id = -1,
.rate = 33333333,
};
};
static struct clk dll_clk = {
- .name = "dll_clk",
- .id = -1,
.ops = &dll_clk_ops,
.parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static struct clk pll_clk = {
- .name = "pll_clk",
- .id = -1,
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
};
.div_mult_table = &div4_div_mult_table,
};
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
- SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+ SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
struct clk div4_clks[DIV4_NR] = {
- [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
- [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
- [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
- [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
- [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
- [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
+ [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
+ [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+ [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+ [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+ [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+ [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
};
enum { DIV4_IRDA, DIV4_ENABLE_NR };
struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
- [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
+ [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
};
enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
- [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
- [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
+ [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
+ [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};
-struct clk div6_clks[] = {
- SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+enum { DIV6_V, DIV6_NR };
+
+struct clk div6_clks[DIV6_NR] = {
+ [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
+};
+
+static struct clk mstp_clks[HWBLK_NR] = {
+ SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
+ SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
+ SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
+ SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
+ SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
+ SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
+ SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
+ SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
+ SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
+
+ SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
+ SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
+
+ SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
+ SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
+ SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
+ SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
+ SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
};
-#define R_CLK &r_clk
-#define P_CLK &div4_clks[DIV4_P]
-#define B_CLK &div4_clks[DIV4_B]
-#define U_CLK &div4_clks[DIV4_U]
-
-static struct clk mstp_clks[] = {
- SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
- SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
- SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0),
- SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
- SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
- SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
- SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
- SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
- SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
-
- SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
- SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
-
- SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0),
- SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
- SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0),
- SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
- SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
- SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
- SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
- SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
- SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
- SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0),
- SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
- SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+ /* main clocks */
+ CLKDEV_CON_ID("rclk", &r_clk),
+ CLKDEV_CON_ID("extal", &extal_clk),
+ CLKDEV_CON_ID("dll_clk", &dll_clk),
+ CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+ /* DIV4 clocks */
+ CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+ CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+ CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+ CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+ CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
+ CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+ CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
+ CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
+ CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
+
+ /* DIV6 clocks */
+ CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+
+ /* MSTP clocks */
+ CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
+ CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
+ {
+ /* TMU0 */
+ .dev_id = "sh_tmu.0",
+ .con_id = "tmu_fck",
+ .clk = &mstp_clks[HWBLK_TMU],
+ }, {
+ /* TMU1 */
+ .dev_id = "sh_tmu.1",
+ .con_id = "tmu_fck",
+ .clk = &mstp_clks[HWBLK_TMU],
+ }, {
+ /* TMU2 */
+ .dev_id = "sh_tmu.2",
+ .con_id = "tmu_fck",
+ .clk = &mstp_clks[HWBLK_TMU],
+ },
+ CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
+ CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
+ CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
+ {
+ /* SCIF0 */
+ .dev_id = "sh-sci.0",
+ .con_id = "sci_fck",
+ .clk = &mstp_clks[HWBLK_SCIF0],
+ }, {
+ /* SCIF1 */
+ .dev_id = "sh-sci.1",
+ .con_id = "sci_fck",
+ .clk = &mstp_clks[HWBLK_SCIF1],
+ }, {
+ /* SCIF2 */
+ .dev_id = "sh-sci.2",
+ .con_id = "sci_fck",
+ .clk = &mstp_clks[HWBLK_SCIF2],
+ },
+ CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
+ CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
+ CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
+ CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
+ CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
+ CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
+ CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
+ CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
+ CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
+ CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
+ CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
+ CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
+ CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
+ CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
};
int __init arch_clk_init(void)
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
DIV4_REPARENT_NR, &div4_table);
if (!ret)
- ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+ ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
- ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+ ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
return ret;
}
git.openpandora.org / pandora-kernel.git / blobdiff