Merge branch 'hwmon-for-linus' of git://jdelvare.pck.nerim.net/jdelvare-2.6

[pandora-kernel.git] / arch / sh / kernel / cpu / init.c

diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 868e68b..4b339a6 100644 (file)
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -3,7 +3,8 @@
  *
  * CPU init code
  *
- * Copyright (C) 2002, 2003  Paul Mundt
+ * Copyright (C) 2002 - 2006  Paul Mundt
+ * Copyright (C) 2003  Richard Curnow
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -11,8 +12,11 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/mm.h>
+#include <asm/mmu_context.h>
 #include <asm/processor.h>
 #include <asm/uaccess.h>
+#include <asm/page.h>
 #include <asm/system.h>
 #include <asm/cacheflush.h>
 #include <asm/cache.h>
@@ -44,28 +48,38 @@ static void __init cache_init(void)
 {
        unsigned long ccr, flags;
 
-       if (cpu_data->type == CPU_SH_NONE)
+       if (current_cpu_data.type == CPU_SH_NONE)
                panic("Unknown CPU");
 
        jump_to_P2();
        ccr = ctrl_inl(CCR);
 
        /*
-        * If the cache is already enabled .. flush it.
+        * At this point we don't know whether the cache is enabled or not - a
+        * bootloader may have enabled it.  There are at least 2 things that
+        * could be dirty in the cache at this point:
+        * 1. kernel command line set up by boot loader
+        * 2. spilled registers from the prolog of this function
+        * => before re-initialising the cache, we must do a purge of the whole
+        * cache out to memory for safety.  As long as nothing is spilled
+        * during the loop to lines that have already been done, this is safe.
+        * - RPC
         */
        if (ccr & CCR_CACHE_ENABLE) {
                unsigned long ways, waysize, addrstart;
 
-               waysize = cpu_data->dcache.sets;
+               waysize = current_cpu_data.dcache.sets;
 
+#ifdef CCR_CACHE_ORA
                /*
                 * If the OC is already in RAM mode, we only have
                 * half of the entries to flush..
                 */
                if (ccr & CCR_CACHE_ORA)
                        waysize >>= 1;
+#endif
 
-               waysize <<= cpu_data->dcache.entry_shift;
+               waysize <<= current_cpu_data.dcache.entry_shift;
 
 #ifdef CCR_CACHE_EMODE
                /* If EMODE is not set, we only have 1 way to flush. */
@@ -73,7 +87,7 @@ static void __init cache_init(void)
                        ways = 1;
                else
 #endif
-                       ways = cpu_data->dcache.ways;
+                       ways = current_cpu_data.dcache.ways;
 
                addrstart = CACHE_OC_ADDRESS_ARRAY;
                do {
@@ -81,10 +95,10 @@ static void __init cache_init(void)
 
                        for (addr = addrstart;
                             addr < addrstart + waysize;
-                            addr += cpu_data->dcache.linesz)
+                            addr += current_cpu_data.dcache.linesz)
                                ctrl_outl(0, addr);
 
-                       addrstart += cpu_data->dcache.way_incr;
+                       addrstart += current_cpu_data.dcache.way_incr;
                } while (--ways);
        }
 
@@ -96,8 +110,10 @@ static void __init cache_init(void)
 
 #ifdef CCR_CACHE_EMODE
        /* Force EMODE if possible */
-       if (cpu_data->dcache.ways > 1)
+       if (current_cpu_data.dcache.ways > 1)
                flags |= CCR_CACHE_EMODE;
+       else
+               flags &= ~CCR_CACHE_EMODE;
 #endif
 
 #ifdef CONFIG_SH_WRITETHROUGH
@@ -111,7 +127,10 @@ static void __init cache_init(void)
 #ifdef CONFIG_SH_OCRAM
        /* Turn on OCRAM -- halve the OC */
        flags |= CCR_CACHE_ORA;
-       cpu_data->dcache.sets >>= 1;
+       current_cpu_data.dcache.sets >>= 1;
+
+       current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
+                                   current_cpu_data.dcache.linesz;
 #endif
 
        ctrl_outl(flags, CCR);
@@ -153,7 +172,7 @@ static void __init dsp_init(void)
 
        /* If the DSP bit is still set, this CPU has a DSP */
        if (sr & SR_DSP)
-               cpu_data->flags |= CPU_HAS_DSP;
+               current_cpu_data.flags |= CPU_HAS_DSP;
 
        /* Now that we've determined the DSP status, clear the DSP bit. */
        release_dsp();
@@ -184,19 +203,29 @@ asmlinkage void __init sh_cpu_init(void)
        /* Init the cache */
        cache_init();
 
+       shm_align_mask = max_t(unsigned long,
+                              current_cpu_data.dcache.way_size - 1,
+                              PAGE_SIZE - 1);
+
        /* Disable the FPU */
        if (fpu_disabled) {
                printk("FPU Disabled\n");
-               cpu_data->flags &= ~CPU_HAS_FPU;
+               current_cpu_data.flags &= ~CPU_HAS_FPU;
                disable_fpu();
        }
 
        /* FPU initialization */
-       if ((cpu_data->flags & CPU_HAS_FPU)) {
+       if ((current_cpu_data.flags & CPU_HAS_FPU)) {
                clear_thread_flag(TIF_USEDFPU);
                clear_used_math();
        }
 
+       /*
+        * Initialize the per-CPU ASID cache very early, since the
+        * TLB flushing routines depend on this being setup.
+        */
+       current_cpu_data.asid_cache = NO_CONTEXT;
+
 #ifdef CONFIG_SH_DSP
        /* Probe for DSP */
        dsp_init();
@@ -204,7 +233,7 @@ asmlinkage void __init sh_cpu_init(void)
        /* Disable the DSP */
        if (dsp_disabled) {
                printk("DSP Disabled\n");
-               cpu_data->flags &= ~CPU_HAS_DSP;
+               current_cpu_data.flags &= ~CPU_HAS_DSP;
                release_dsp();
        }
 #endif
@@ -219,4 +248,3 @@ asmlinkage void __init sh_cpu_init(void)
        ubc_wakeup();
 #endif
 }
-