-/* the exported API, in addition to clk_set_rate */
-/**
- * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
- * @clk: clock source
- * @rate: desired clock rate in Hz
- * @algo_id: algorithm id to be passed down to ops->set_rate
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
-
-enum clk_sh_algo_id {
- NO_CHANGE = 0,
-
- IUS_N1_N1,
- IUS_322,
- IUS_522,
- IUS_N11,
-
- SB_N1,
-
- SB3_N1,
- SB3_32,
- SB3_43,
- SB3_54,
-
- BP_N1,
-
- IP_N1,
-};
-
-struct clk_div_mult_table {
- unsigned int *divisors;
- unsigned int nr_divisors;
- unsigned int *multipliers;
- unsigned int nr_multipliers;
-};
-
-struct cpufreq_frequency_table;
-void clk_rate_table_build(struct clk *clk,
- struct cpufreq_frequency_table *freq_table,
- int nr_freqs,
- struct clk_div_mult_table *src_table,
- unsigned long *bitmap);
-
-long clk_rate_table_round(struct clk *clk,
- struct cpufreq_frequency_table *freq_table,
- unsigned long rate);
-
-int clk_rate_table_find(struct clk *clk,
- struct cpufreq_frequency_table *freq_table,
- unsigned long rate);
-
-#define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \
- _enable_bit, _flags) \
-{ \
- .name = _name, \
- .id = _id, \
- .parent = _parent, \
- .enable_reg = (void __iomem *)_enable_reg, \
- .enable_bit = _enable_bit, \
- .flags = _flags, \
-}
-
-int sh_clk_mstp32_register(struct clk *clks, int nr);
-
-#define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \
-{ \
- .name = _name, \
- .parent = _parent, \
- .enable_reg = (void __iomem *)_reg, \
- .enable_bit = _shift, \
- .arch_flags = _div_bitmap, \
- .flags = _flags, \
-}
-
-struct clk_div4_table {
- struct clk_div_mult_table *div_mult_table;
- void (*kick)(struct clk *clk);
-};
-
-int sh_clk_div4_register(struct clk *clks, int nr,
- struct clk_div4_table *table);
-int sh_clk_div4_enable_register(struct clk *clks, int nr,
- struct clk_div4_table *table);
-int sh_clk_div4_reparent_register(struct clk *clks, int nr,
- struct clk_div4_table *table);
-
-#define SH_CLK_DIV6(_name, _parent, _reg, _flags) \
-{ \
- .name = _name, \
- .parent = _parent, \
- .enable_reg = (void __iomem *)_reg, \
- .flags = _flags, \
-}
-
-int sh_clk_div6_register(struct clk *clks, int nr);