Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6

[pandora-kernel.git] / arch / sh / drivers / pci / ops-sh7786.c

diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c
index 48f594b..1284210 100644 (file)
--- a/arch/sh/drivers/pci/ops-sh7786.c
+++ b/arch/sh/drivers/pci/ops-sh7786.c
@@ -1,7 +1,7 @@
 /*
  * Generic SH7786 PCI-Express operations.
  *
- *  Copyright (C) 2009  Paul Mundt
+ *  Copyright (C) 2009 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License v2. See the file "COPYING" in the main directory of this archive
@@ -19,37 +19,72 @@ enum {
        PCI_ACCESS_WRITE,
 };
 
-static DEFINE_SPINLOCK(sh7786_pcie_lock);
-
 static int sh7786_pcie_config_access(unsigned char access_type,
                struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
 {
        struct pci_channel *chan = bus->sysdata;
-       int dev, func;
+       int dev, func, type, reg;
 
        dev = PCI_SLOT(devfn);
        func = PCI_FUNC(devfn);
+       type = !!bus->parent;
+       reg = where & ~3;
 
        if (bus->number > 255 || dev > 31 || func > 7)
                return PCIBIOS_FUNC_NOT_SUPPORTED;
-       if (devfn)
-               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       /*
+        * While each channel has its own memory-mapped extended config
+        * space, it's generally only accessible when in endpoint mode.
+        * When in root complex mode, the controller is unable to target
+        * itself with either type 0 or type 1 accesses, and indeed, any
+        * controller initiated target transfer to its own config space
+        * result in a completer abort.
+        *
+        * Each channel effectively only supports a single device, but as
+        * the same channel <-> device access works for any PCI_SLOT()
+        * value, we cheat a bit here and bind the controller's config
+        * space to devfn 0 in order to enable self-enumeration. In this
+        * case the regular PAR/PDR path is sidelined and the mangled
+        * config access itself is initiated as a SuperHyway transaction.
+        */
+       if (pci_is_root_bus(bus)) {
+               if (dev == 0) {
+                       if (access_type == PCI_ACCESS_READ)
+                               *data = pci_read_reg(chan, PCI_REG(reg));
+                       else
+                               pci_write_reg(chan, *data, PCI_REG(reg));
+
+                       return PCIBIOS_SUCCESSFUL;
+               } else if (dev > 1)
+                       return PCIBIOS_DEVICE_NOT_FOUND;
+       }
+
+       /* Clear errors */
+       pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
 
        /* Set the PIO address */
        pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
-                               (func << 16) | (where & ~3), SH4A_PCIEPAR);
+                               (func << 16) | reg, SH4A_PCIEPAR);
 
        /* Enable the configuration access */
-       pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
+       pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
+
+       /* Check for errors */
+       if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       /* Check for master and target aborts */
+       if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
+               return PCIBIOS_DEVICE_NOT_FOUND;
 
        if (access_type == PCI_ACCESS_READ)
                *data = pci_read_reg(chan, SH4A_PCIEPDR);
        else
                pci_write_reg(chan, *data, SH4A_PCIEPDR);
 
-       /* Check for master and target aborts */
-       if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
-               return PCIBIOS_DEVICE_NOT_FOUND;
+       /* Disable the configuration access */
+       pci_write_reg(chan, 0, SH4A_PCIEPCTLR);
 
        return PCIBIOS_SUCCESSFUL;
 }
@@ -66,11 +101,13 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
        else if ((size == 4) && (where & 3))
                return PCIBIOS_BAD_REGISTER_NUMBER;
 
-       spin_lock_irqsave(&sh7786_pcie_lock, flags);
+       raw_spin_lock_irqsave(&pci_config_lock, flags);
        ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
                                        devfn, where, &data);
-       if (ret != PCIBIOS_SUCCESSFUL)
+       if (ret != PCIBIOS_SUCCESSFUL) {
+               *val = 0xffffffff;
                goto out;
+       }
 
        if (size == 1)
                *val = (data >> ((where & 3) << 3)) & 0xff;
@@ -84,7 +121,7 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
                devfn, where, size, (unsigned long)*val);
 
 out:
-       spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
+       raw_spin_unlock_irqrestore(&pci_config_lock, flags);
        return ret;
 }
 
@@ -100,7 +137,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
        else if ((size == 4) && (where & 3))
                return PCIBIOS_BAD_REGISTER_NUMBER;
 
-       spin_lock_irqsave(&sh7786_pcie_lock, flags);
+       raw_spin_lock_irqsave(&pci_config_lock, flags);
        ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
                                        devfn, where, &data);
        if (ret != PCIBIOS_SUCCESSFUL)
@@ -124,7 +161,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
        ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
                                        devfn, where, &data);
 out:
-       spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
+       raw_spin_unlock_irqrestore(&pci_config_lock, flags);
        return ret;
 }