Merge branch 'linux-2.6'

[pandora-kernel.git] / arch / powerpc / sysdev / ipic.c

diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index e898ff4..ae0dbf4 100644 (file)
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -30,11 +30,67 @@
 #include "ipic.h"
 
 static struct ipic * primary_ipic;
+static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
 static DEFINE_SPINLOCK(ipic_lock);
 
 static struct ipic_info ipic_info[] = {
+       [1] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 16,
+               .prio_mask = 0,
+       },
+       [2] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 17,
+               .prio_mask = 1,
+       },
+       [3] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 18,
+               .prio_mask = 2,
+       },
+       [4] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 19,
+               .prio_mask = 3,
+       },
+       [5] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 20,
+               .prio_mask = 4,
+       },
+       [6] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 21,
+               .prio_mask = 5,
+       },
+       [7] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 22,
+               .prio_mask = 6,
+       },
+       [8] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_C,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 23,
+               .prio_mask = 7,
+       },
        [9] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_D,
                .force  = IPIC_SIFCR_H,
@@ -42,7 +98,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 0,
        },
        [10] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_D,
                .force  = IPIC_SIFCR_H,
@@ -50,15 +105,27 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 1,
        },
        [11] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_D,
                .force  = IPIC_SIFCR_H,
                .bit    = 26,
                .prio_mask = 2,
        },
+       [12] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_D,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 27,
+               .prio_mask = 3,
+       },
+       [13] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_D,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 28,
+               .prio_mask = 4,
+       },
        [14] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_D,
                .force  = IPIC_SIFCR_H,
@@ -66,7 +133,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 5,
        },
        [15] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_D,
                .force  = IPIC_SIFCR_H,
@@ -74,7 +140,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 6,
        },
        [16] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_D,
                .force  = IPIC_SIFCR_H,
@@ -82,7 +147,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 7,
        },
        [17] = {
-               .pend   = IPIC_SEPNR,
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SEFCR,
@@ -90,7 +155,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 5,
        },
        [18] = {
-               .pend   = IPIC_SEPNR,
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SEFCR,
@@ -98,7 +163,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 6,
        },
        [19] = {
-               .pend   = IPIC_SEPNR,
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SEFCR,
@@ -106,7 +171,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 7,
        },
        [20] = {
-               .pend   = IPIC_SEPNR,
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SEFCR,
@@ -114,7 +179,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 4,
        },
        [21] = {
-               .pend   = IPIC_SEPNR,
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SEFCR,
@@ -122,7 +187,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 5,
        },
        [22] = {
-               .pend   = IPIC_SEPNR,
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SEFCR,
@@ -130,7 +195,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 6,
        },
        [23] = {
-               .pend   = IPIC_SEPNR,
+               .ack    = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SEFCR,
@@ -138,7 +203,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 7,
        },
        [32] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
@@ -146,7 +210,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 0,
        },
        [33] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
@@ -154,7 +217,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 1,
        },
        [34] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
@@ -162,7 +224,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 2,
        },
        [35] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
@@ -170,7 +231,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 3,
        },
        [36] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
@@ -178,7 +238,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 4,
        },
        [37] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
@@ -186,7 +245,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 5,
        },
        [38] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
@@ -194,15 +252,69 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 6,
        },
        [39] = {
-               .pend   = IPIC_SIPNR_H,
                .mask   = IPIC_SIMSR_H,
                .prio   = IPIC_SIPRR_A,
                .force  = IPIC_SIFCR_H,
                .bit    = 7,
                .prio_mask = 7,
        },
+       [40] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 8,
+               .prio_mask = 0,
+       },
+       [41] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 9,
+               .prio_mask = 1,
+       },
+       [42] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 10,
+               .prio_mask = 2,
+       },
+       [43] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 11,
+               .prio_mask = 3,
+       },
+       [44] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 12,
+               .prio_mask = 4,
+       },
+       [45] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 13,
+               .prio_mask = 5,
+       },
+       [46] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 14,
+               .prio_mask = 6,
+       },
+       [47] = {
+               .mask   = IPIC_SIMSR_H,
+               .prio   = IPIC_SIPRR_B,
+               .force  = IPIC_SIFCR_H,
+               .bit    = 15,
+               .prio_mask = 7,
+       },
        [48] = {
-               .pend   = IPIC_SEPNR,
                .mask   = IPIC_SEMSR,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SEFCR,
@@ -210,7 +322,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 4,
        },
        [64] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -218,7 +329,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 0,
        },
        [65] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -226,7 +336,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 1,
        },
        [66] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -234,7 +343,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 2,
        },
        [67] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -242,7 +350,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 3,
        },
        [68] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -250,7 +357,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 0,
        },
        [69] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -258,7 +364,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 1,
        },
        [70] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -266,7 +371,6 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 2,
        },
        [71] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -274,96 +378,131 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 3,
        },
        [72] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 8,
        },
        [73] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 9,
        },
        [74] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 10,
        },
        [75] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 11,
        },
        [76] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 12,
        },
        [77] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 13,
        },
        [78] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 14,
        },
        [79] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 15,
        },
        [80] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 16,
        },
+       [81] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 17,
+       },
+       [82] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 18,
+       },
+       [83] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 19,
+       },
        [84] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 20,
        },
        [85] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 21,
        },
+       [86] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 22,
+       },
+       [87] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 23,
+       },
+       [88] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 24,
+       },
+       [89] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 25,
+       },
        [90] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 26,
        },
        [91] = {
-               .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 27,
        },
+       [94] = {
+               .mask   = IPIC_SIMSR_L,
+               .prio   = 0,
+               .force  = IPIC_SIFCR_L,
+               .bit    = 30,
+       },
 };
 
 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
@@ -412,6 +551,10 @@ static void ipic_mask_irq(unsigned int virq)
        temp &= ~(1 << (31 - ipic_info[src].bit));
        ipic_write(ipic->regs, ipic_info[src].mask, temp);
 
+       /* mb() can't guarantee that masking is finished.  But it does finish
+        * for nearly all cases. */
+       mb();
+
        spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
@@ -424,9 +567,13 @@ static void ipic_ack_irq(unsigned int virq)
 
        spin_lock_irqsave(&ipic_lock, flags);
 
-       temp = ipic_read(ipic->regs, ipic_info[src].pend);
+       temp = ipic_read(ipic->regs, ipic_info[src].ack);
        temp |= (1 << (31 - ipic_info[src].bit));
-       ipic_write(ipic->regs, ipic_info[src].pend, temp);
+       ipic_write(ipic->regs, ipic_info[src].ack, temp);
+
+       /* mb() can't guarantee that ack is finished.  But it does finish
+        * for nearly all cases. */
+       mb();
 
        spin_unlock_irqrestore(&ipic_lock, flags);
 }
@@ -444,9 +591,13 @@ static void ipic_mask_irq_and_ack(unsigned int virq)
        temp &= ~(1 << (31 - ipic_info[src].bit));
        ipic_write(ipic->regs, ipic_info[src].mask, temp);
 
-       temp = ipic_read(ipic->regs, ipic_info[src].pend);
+       temp = ipic_read(ipic->regs, ipic_info[src].ack);
        temp |= (1 << (31 - ipic_info[src].bit));
-       ipic_write(ipic->regs, ipic_info[src].pend, temp);
+       ipic_write(ipic->regs, ipic_info[src].ack, temp);
+
+       /* mb() can't guarantee that ack is finished.  But it does finish
+        * for nearly all cases. */
+       mb();
 
        spin_unlock_irqrestore(&ipic_lock, flags);
 }
@@ -468,14 +619,22 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
                        flow_type);
                return -EINVAL;
        }
+       /* ipic supports only edge mode on external interrupts */
+       if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
+               printk(KERN_ERR "ipic: edge sense not supported on internal "
+                               "interrupts\n");
+               return -EINVAL;
+       }
 
        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
        if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
                desc->status |= IRQ_LEVEL;
                desc->handle_irq = handle_level_irq;
+               desc->chip = &ipic_level_irq_chip;
        } else {
                desc->handle_irq = handle_edge_irq;
+               desc->chip = &ipic_edge_irq_chip;
        }
 
        /* only EXT IRQ senses are programmable on ipic
@@ -500,7 +659,16 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
        return 0;
 }
 
-static struct irq_chip ipic_irq_chip = {
+/* level interrupts and edge interrupts have different ack operations */
+static struct irq_chip ipic_level_irq_chip = {
+       .typename       = " IPIC  ",
+       .unmask         = ipic_unmask_irq,
+       .mask           = ipic_mask_irq,
+       .mask_ack       = ipic_mask_irq,
+       .set_type       = ipic_set_irq_type,
+};
+
+static struct irq_chip ipic_edge_irq_chip = {
        .typename       = " IPIC  ",
        .unmask         = ipic_unmask_irq,
        .mask           = ipic_mask_irq,
@@ -519,13 +687,9 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq,
                         irq_hw_number_t hw)
 {
        struct ipic *ipic = h->host_data;
-       struct irq_chip *chip;
-
-       /* Default chip */
-       chip = &ipic->hc_irq;
 
        set_irq_chip_data(virq, ipic);
-       set_irq_chip_and_handler(virq, chip, handle_level_irq);
+       set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
 
        /* Set default irq type */
        set_irq_type(virq, IRQ_TYPE_NONE);
@@ -584,7 +748,6 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
        ipic->regs = ioremap(res.start, res.end - res.start + 1);
 
        ipic->irqhost->host_data = ipic;
-       ipic->hc_irq = ipic_irq_chip;
 
        /* init hw */
        ipic_write(ipic->regs, IPIC_SICNR, 0x0);
@@ -593,6 +756,10 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
         * configure SICFR accordingly */
        if (flags & IPIC_SPREADMODE_GRP_A)
                temp |= SICFR_IPSA;
+       if (flags & IPIC_SPREADMODE_GRP_B)
+               temp |= SICFR_IPSB;
+       if (flags & IPIC_SPREADMODE_GRP_C)
+               temp |= SICFR_IPSC;
        if (flags & IPIC_SPREADMODE_GRP_D)
                temp |= SICFR_IPSD;
        if (flags & IPIC_SPREADMODE_MIX_A)
@@ -600,7 +767,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
        if (flags & IPIC_SPREADMODE_MIX_B)
                temp |= SICFR_MPSB;
 
-       ipic_write(ipic->regs, IPIC_SICNR, temp);
+       ipic_write(ipic->regs, IPIC_SICFR, temp);
 
        /* handle MCP route */
        temp = 0;
@@ -672,10 +839,12 @@ void ipic_set_highest_priority(unsigned int virq)
 
 void ipic_set_default_priority(void)
 {
-       ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
-       ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
-       ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
-       ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
+       ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
+       ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
+       ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
+       ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
+       ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
+       ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
 }
 
 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)