git.openpandora.org
/
pandora-kernel.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Merge branch 'dev' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4
[pandora-kernel.git]
/
arch
/
powerpc
/
platforms
/
cell
/
spufs
/
hw_ops.c
diff --git
a/arch/powerpc/platforms/cell/spufs/hw_ops.c
b/arch/powerpc/platforms/cell/spufs/hw_ops.c
index
a7767e3
..
8655c4c
100644
(file)
--- a/
arch/powerpc/platforms/cell/spufs/hw_ops.c
+++ b/
arch/powerpc/platforms/cell/spufs/hw_ops.c
@@
-18,7
+18,6
@@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#include <linux/module.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
@@
-76,16
+75,18
@@
static unsigned int spu_hw_mbox_stat_poll(struct spu_context *ctx,
if (stat & 0xff0000)
ret |= POLLIN | POLLRDNORM;
else {
if (stat & 0xff0000)
ret |= POLLIN | POLLRDNORM;
else {
- spu_int_stat_clear(spu, 2,
0x1
);
- spu_int_mask_or(spu, 2,
0x1
);
+ spu_int_stat_clear(spu, 2,
CLASS2_MAILBOX_INTR
);
+ spu_int_mask_or(spu, 2,
CLASS2_ENABLE_MAILBOX_INTR
);
}
}
if (events & (POLLOUT | POLLWRNORM)) {
if (stat & 0x00ff00)
ret = POLLOUT | POLLWRNORM;
else {
}
}
if (events & (POLLOUT | POLLWRNORM)) {
if (stat & 0x00ff00)
ret = POLLOUT | POLLWRNORM;
else {
- spu_int_stat_clear(spu, 2, 0x10);
- spu_int_mask_or(spu, 2, 0x10);
+ spu_int_stat_clear(spu, 2,
+ CLASS2_MAILBOX_THRESHOLD_INTR);
+ spu_int_mask_or(spu, 2,
+ CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
}
}
spin_unlock_irq(&spu->register_lock);
}
}
spin_unlock_irq(&spu->register_lock);
@@
-106,7
+107,7
@@
static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data)
ret = 4;
} else {
/* make sure we get woken up by the interrupt */
ret = 4;
} else {
/* make sure we get woken up by the interrupt */
- spu_int_mask_or(spu, 2,
0x1
);
+ spu_int_mask_or(spu, 2,
CLASS2_ENABLE_MAILBOX_INTR
);
ret = 0;
}
spin_unlock_irq(&spu->register_lock);
ret = 0;
}
spin_unlock_irq(&spu->register_lock);
@@
-127,7
+128,7
@@
static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
} else {
/* make sure we get woken up by the interrupt when space
becomes available */
} else {
/* make sure we get woken up by the interrupt when space
becomes available */
- spu_int_mask_or(spu, 2,
0x10
);
+ spu_int_mask_or(spu, 2,
CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR
);
ret = 0;
}
spin_unlock_irq(&spu->register_lock);
ret = 0;
}
spin_unlock_irq(&spu->register_lock);