Merge branch 'dev' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4

[pandora-kernel.git] / arch / powerpc / platforms / cell / spufs / hw_ops.c

diff --git a/arch/powerpc/platforms/cell/spufs/hw_ops.c b/arch/powerpc/platforms/cell/spufs/hw_ops.c
index ae42e03..8655c4c 100644 (file)
--- a/arch/powerpc/platforms/cell/spufs/hw_ops.c
+++ b/arch/powerpc/platforms/cell/spufs/hw_ops.c
@@ -18,14 +18,12 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/poll.h>
 #include <linux/smp.h>
-#include <linux/smp_lock.h>
 #include <linux/stddef.h>
 #include <linux/unistd.h>
 
@@ -77,16 +75,18 @@ static unsigned int spu_hw_mbox_stat_poll(struct spu_context *ctx,
                if (stat & 0xff0000)
                        ret |= POLLIN | POLLRDNORM;
                else {
-                       spu_int_stat_clear(spu, 2, 0x1);
-                       spu_int_mask_or(spu, 2, 0x1);
+                       spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);
+                       spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
                }
        }
        if (events & (POLLOUT | POLLWRNORM)) {
                if (stat & 0x00ff00)
                        ret = POLLOUT | POLLWRNORM;
                else {
-                       spu_int_stat_clear(spu, 2, 0x10);
-                       spu_int_mask_or(spu, 2, 0x10);
+                       spu_int_stat_clear(spu, 2,
+                                       CLASS2_MAILBOX_THRESHOLD_INTR);
+                       spu_int_mask_or(spu, 2,
+                                       CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
                }
        }
        spin_unlock_irq(&spu->register_lock);
@@ -107,7 +107,7 @@ static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data)
                ret = 4;
        } else {
                /* make sure we get woken up by the interrupt */
-               spu_int_mask_or(spu, 2, 0x1);
+               spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
                ret = 0;
        }
        spin_unlock_irq(&spu->register_lock);
@@ -128,7 +128,7 @@ static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
        } else {
                /* make sure we get woken up by the interrupt when space
                   becomes available */
-               spu_int_mask_or(spu, 2, 0x10);
+               spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
                ret = 0;
        }
        spin_unlock_irq(&spu->register_lock);
@@ -207,6 +207,11 @@ static char *spu_hw_get_ls(struct spu_context *ctx)
        return ctx->spu->local_store;
 }
 
+static void spu_hw_privcntl_write(struct spu_context *ctx, u64 val)
+{
+       out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
+}
+
 static u32 spu_hw_runcntl_read(struct spu_context *ctx)
 {
        return in_be32(&ctx->spu->problem->spu_runcntl_RW);
@@ -216,11 +221,21 @@ static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
 {
        spin_lock_irq(&ctx->spu->register_lock);
        if (val & SPU_RUNCNTL_ISOLATE)
-               out_be64(&ctx->spu->priv2->spu_privcntl_RW, 4LL);
+               spu_hw_privcntl_write(ctx,
+                       SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK);
        out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
        spin_unlock_irq(&ctx->spu->register_lock);
 }
 
+static void spu_hw_runcntl_stop(struct spu_context *ctx)
+{
+       spin_lock_irq(&ctx->spu->register_lock);
+       out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
+       while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
+               cpu_relax();
+       spin_unlock_irq(&ctx->spu->register_lock);
+}
+
 static void spu_hw_master_start(struct spu_context *ctx)
 {
        struct spu *spu = ctx->spu;
@@ -296,6 +311,14 @@ static int spu_hw_send_mfc_command(struct spu_context *ctx,
        }
 }
 
+static void spu_hw_restart_dma(struct spu_context *ctx)
+{
+       struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;
+
+       if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))
+               out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
+}
+
 struct spu_context_ops spu_hw_ops = {
        .mbox_read = spu_hw_mbox_read,
        .mbox_stat_read = spu_hw_mbox_stat_read,
@@ -312,12 +335,15 @@ struct spu_context_ops spu_hw_ops = {
        .npc_write = spu_hw_npc_write,
        .status_read = spu_hw_status_read,
        .get_ls = spu_hw_get_ls,
+       .privcntl_write = spu_hw_privcntl_write,
        .runcntl_read = spu_hw_runcntl_read,
        .runcntl_write = spu_hw_runcntl_write,
+       .runcntl_stop = spu_hw_runcntl_stop,
        .master_start = spu_hw_master_start,
        .master_stop = spu_hw_master_stop,
        .set_mfc_query = spu_hw_set_mfc_query,
        .read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
        .get_mfc_free_elements = spu_hw_get_mfc_free_elements,
        .send_mfc_command = spu_hw_send_mfc_command,
+       .restart_dma = spu_hw_restart_dma,
 };