powerpc: FPGA support for GE Fanuc SBC610

[pandora-kernel.git] / arch / powerpc / platforms / 86xx / gef_sbc610.c

diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index ee21500..821c45f 100644 (file)
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -39,6 +39,7 @@
 #include <sysdev/fsl_soc.h>
 
 #include "mpc86xx.h"
+#include "gef_pic.h"
 
 #undef DEBUG
 
@@ -48,8 +49,31 @@
 #define DBG (fmt...) do { } while (0)
 #endif
 
+void __iomem *sbc610_regs;
+
+static void __init gef_sbc610_init_irq(void)
+{
+       struct device_node *cascade_node = NULL;
+
+       mpc86xx_init_irq();
+
+       /*
+        * There is a simple interrupt handler in the main FPGA, this needs
+        * to be cascaded into the MPIC
+        */
+       cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
+       if (!cascade_node) {
+               printk(KERN_WARNING "SBC610: No FPGA PIC\n");
+               return;
+       }
+
+       gef_pic_init(cascade_node);
+       of_node_put(cascade_node);
+}
+
 static void __init gef_sbc610_setup_arch(void)
 {
+       struct device_node *regs;
 #ifdef CONFIG_PCI
        struct device_node *np;
 
@@ -63,8 +87,43 @@ static void __init gef_sbc610_setup_arch(void)
 #ifdef CONFIG_SMP
        mpc86xx_smp_init();
 #endif
+
+       /* Remap basic board registers */
+       regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
+       if (regs) {
+               sbc610_regs = of_iomap(regs, 0);
+               if (sbc610_regs == NULL)
+                       printk(KERN_WARNING "Unable to map board registers\n");
+               of_node_put(regs);
+       }
+}
+
+/* Return the PCB revision */
+static unsigned int gef_sbc610_get_pcb_rev(void)
+{
+       unsigned int reg;
+
+       reg = ioread32(sbc610_regs);
+       return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int gef_sbc610_get_board_rev(void)
+{
+       unsigned int reg;
+
+       reg = ioread32(sbc610_regs);
+       return (reg >> 16) & 0xff;
 }
 
+/* Return the FPGA revision */
+static unsigned int gef_sbc610_get_fpga_rev(void)
+{
+       unsigned int reg;
+
+       reg = ioread32(sbc610_regs);
+       return (reg >> 24) & 0xf;
+}
 
 static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 {
@@ -73,6 +132,10 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 
        seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 
+       seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
+               ('A' + gef_sbc610_get_board_rev() - 1));
+       seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
+
        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
        seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 }
@@ -145,7 +208,7 @@ define_machine(gef_sbc610) {
        .name                   = "GE Fanuc SBC610",
        .probe                  = gef_sbc610_probe,
        .setup_arch             = gef_sbc610_setup_arch,
-       .init_IRQ               = mpc86xx_init_irq,
+       .init_IRQ               = gef_sbc610_init_irq,
        .show_cpuinfo           = gef_sbc610_show_cpuinfo,
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,