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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[pandora-kernel.git]
/
arch
/
powerpc
/
platforms
/
85xx
/
p1022_ds.c
diff --git
a/arch/powerpc/platforms/85xx/p1022_ds.c
b/arch/powerpc/platforms/85xx/p1022_ds.c
index
7eb5c40
..
266b3aa
100644
(file)
--- a/
arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/
arch/powerpc/platforms/85xx/p1022_ds.c
@@
-129,6
+129,7
@@
static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base)
static void p1022ds_set_monitor_port(int monitor_port)
{
struct device_node *pixis_node;
static void p1022ds_set_monitor_port(int monitor_port)
{
struct device_node *pixis_node;
+ void __iomem *pixis;
u8 __iomem *brdcfg1;
pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
u8 __iomem *brdcfg1;
pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
@@
-137,12
+138,12
@@
static void p1022ds_set_monitor_port(int monitor_port)
return;
}
return;
}
-
brdcfg1
= of_iomap(pixis_node, 0);
- if (!
brdcfg1
) {
+
pixis
= of_iomap(pixis_node, 0);
+ if (!
pixis
) {
pr_err("p1022ds: could not map ngPIXIS registers\n");
return;
}
pr_err("p1022ds: could not map ngPIXIS registers\n");
return;
}
- brdcfg1
+= 9;
/* BRDCFG1 is at offset 9 in the ngPIXIS */
+ brdcfg1
= pixis + 9;
/* BRDCFG1 is at offset 9 in the ngPIXIS */
switch (monitor_port) {
case 0: /* DVI */
switch (monitor_port) {
case 0: /* DVI */
@@
-158,6
+159,8
@@
static void p1022ds_set_monitor_port(int monitor_port)
default:
pr_err("p1022ds: unsupported monitor port %i\n", monitor_port);
}
default:
pr_err("p1022ds: unsupported monitor port %i\n", monitor_port);
}
+
+ iounmap(pixis);
}
/**
}
/**
@@
-192,8
+195,13
@@
void p1022ds_set_pixel_clock(unsigned int pixclock)
do_div(temp, pixclock);
freq = temp;
do_div(temp, pixclock);
freq = temp;
- /* pixclk is the ratio of the platform clock to the pixel clock */
+ /*
+ * 'pxclk' is the ratio of the platform clock to the pixel clock.
+ * This number is programmed into the CLKDVDR register, and the valid
+ * range of values is 2-255.
+ */
pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
+ pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
clrbits32(&guts->clkdvdr,
/* Disable the pixel clock, and set it to non-inverted and no delay */
clrbits32(&guts->clkdvdr,
@@
-201,6
+209,8
@@
void p1022ds_set_pixel_clock(unsigned int pixclock)
/* Enable the clock and set the pxclk */
setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
/* Enable the clock and set the pxclk */
setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+
+ iounmap(guts);
}
/**
}
/**