Merge commit 'v2.6.39-rc3' into for-2.6.39

[pandora-kernel.git] / arch / powerpc / mm / tlb_low_64e.S

diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index 8526bd9..af08922 100644 (file)
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -192,7 +192,7 @@ normal_tlb_miss:
        or      r10,r15,r14
 
 BEGIN_MMU_FTR_SECTION
-       /* Set the TLB reservation and seach for existing entry. Then load
+       /* Set the TLB reservation and search for existing entry. Then load
         * the entry.
         */
        PPC_TLBSRX_DOT(0,r16)
@@ -425,13 +425,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
 
 virt_page_table_tlb_miss_fault:
        /* If we fault here, things are a little bit tricky. We need to call
-        * either data or instruction store fault, and we need to retreive
+        * either data or instruction store fault, and we need to retrieve
         * the original fault address and ESR (for data).
         *
         * The thing is, we know that in normal circumstances, this is
         * always called as a second level tlb miss for SW load or as a first
         * level TLB miss for HW load, so we should be able to peek at the
-        * relevant informations in the first exception frame in the PACA.
+        * relevant information in the first exception frame in the PACA.
         *
         * However, we do need to double check that, because we may just hit
         * a stray kernel pointer or a userland attack trying to hit those