Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...

[pandora-kernel.git] / arch / powerpc / include / asm / fsl_lbc.h

diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a210..5c1bf34 100644 (file)
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
 /* Freescale Local Bus Controller
  *
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright © 2006-2007, 2010 Freescale Semiconductor
  *
  * Authors: Nick Spence <nick.spence@freescale.com>,
  *          Scott Wood <scottwood@freescale.com>
+ *          Jack Lan <jack.lan@freescale.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,6 +27,8 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <linux/io.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
 
 struct fsl_lbc_bank {
        __be32 br;             /**< Base Register  */
@@ -125,13 +128,23 @@ struct fsl_lbc_regs {
 #define LTESR_ATMW 0x00800000
 #define LTESR_ATMR 0x00400000
 #define LTESR_CS   0x00080000
+#define LTESR_UPM  0x00000002
 #define LTESR_CC   0x00000001
 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+                        | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+                        | LTESR_CC)
+#define LTESR_CLEAR    0xFFFFFFFF
+#define LTECCR_CLEAR   0xFFFFFFFF
+#define LTESR_STATUS   LTESR_MASK
+#define LTEIR_ENABLE   LTESR_MASK
+#define LTEDR_ENABLE   0x00000000
        __be32 ltedr;           /**< Transfer Error Disable Register */
        __be32 lteir;           /**< Transfer Error Interrupt Register */
        __be32 lteatr;          /**< Transfer Error Attributes Register */
        __be32 ltear;           /**< Transfer Error Address Register */
-       u8 res6[0xC];
+       __be32 lteccr;          /**< Transfer Error ECC Register */
+       u8 res6[0x8];
        __be32 lbcr;            /**< Configuration Register */
 #define LBCR_LDIS  0x80000000
 #define LBCR_LDIS_SHIFT    31
@@ -235,6 +248,7 @@ struct fsl_upm {
        int width;
 };
 
+extern u32 fsl_lbc_addr(phys_addr_t addr_base);
 extern int fsl_lbc_find(phys_addr_t addr_base);
 extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
 
@@ -265,7 +279,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
                cpu_relax();
 }
 
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+       /* device info */
+       struct device                   *dev;
+       struct fsl_lbc_regs __iomem     *regs;
+       int                             irq;
+       wait_queue_head_t               irq_wait;
+       spinlock_t                      lock;
+       void                            *nand;
+
+       /* status read from LTESR by irq handler */
+       unsigned int                    irq_status;
+};
+
 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
                               u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
 
 #endif /* __ASM_FSL_LBC_H */