timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>; // CCSRBAR 1M
+ reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8555-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
- interrupts = <2 2>;
+ interrupts = <12 2>;
};
l2-cache-controller@20000 {
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
- interrupts = <0 2>;
+ interrupts = <10 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3000 100>;
- interrupts = <1b 2>;
+ interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
reg = <24520 20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
- interrupts = <35 0>;
+ interrupts = <5 1>;
reg = <0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
- interrupts = <35 0>;
+ interrupts = <5 1>;
reg = <1>;
device_type = "ethernet-phy";
};
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
- local-mac-address = [ 00 E0 0C 00 73 00 ];
- interrupts = <0d 2 0e 2 12 2>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <1d 2 1e 2 22 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
- local-mac-address = [ 00 E0 0C 00 73 01 ];
- interrupts = <13 2 14 2 18 2>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 2 24 2 28 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
compatible = "ns16550";
reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <1a 2>;
+ interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
compatible = "ns16550";
reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <1a 2>;
+ interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
- pci1: pci@8000 {
- interrupt-map-mask = <1f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x10 */
- 08000 0 0 1 &mpic 30 1
- 08000 0 0 2 &mpic 31 1
- 08000 0 0 3 &mpic 32 1
- 08000 0 0 4 &mpic 33 1
-
- /* IDSEL 0x11 */
- 08800 0 0 1 &mpic 30 1
- 08800 0 0 2 &mpic 31 1
- 08800 0 0 3 &mpic 32 1
- 08800 0 0 4 &mpic 33 1
-
- /* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 30 1
- 09000 0 0 2 &mpic 31 1
- 09000 0 0 3 &mpic 32 1
- 09000 0 0 4 &mpic 33 1
-
- /* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 31 1
- 09800 0 0 2 &mpic 32 1
- 09800 0 0 3 &mpic 33 1
- 09800 0 0 4 &mpic 30 1
-
- /* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 32 1
- 0a000 0 0 2 &mpic 33 1
- 0a000 0 0 3 &mpic 30 1
- 0a000 0 0 4 &mpic 31 1
-
- /* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 33 1
- 0a800 0 0 2 &mpic 30 1
- 0a800 0 0 3 &mpic 31 1
- 0a800 0 0 4 &mpic 32 1
-
- /* Bus 1 (Tundra Bridge) */
- /* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 30 1
- 19000 0 0 2 &mpic 31 1
- 19000 0 0 3 &mpic 32 1
- 19000 0 0 4 &mpic 33 1>;
- interrupt-parent = <&mpic>;
- interrupts = <08 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "85xx";
- device_type = "pci";
-
- i8259@19000 {
- clock-frequency = <0>;
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+
+ cpm@919c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
+ reg = <919c0 30>;
+ ranges;
+
+ muram@80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 80000 10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 2000 9000 1000>;
+ };
+ };
+
+ brg@919f0 {
+ compatible = "fsl,mpc8555-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <919f0 10 915f0 10>;
+ };
+
+ cpmpic: pic@90c00 {
interrupt-controller;
- device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- big-endian;
- interrupts = <1>;
- interrupt-parent = <&pci1>;
+ interrupts = <2e 2>;
+ interrupt-parent = <&mpic>;
+ reg = <90c00 80>;
+ compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
};
};
+ };
- pci@9000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
+ pci1: pci@e0008000 {
+ interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map = <
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic 3b 1
- a800 0 0 2 &mpic 3b 1
- a800 0 0 3 &mpic 3b 1
- a800 0 0 4 &mpic 3b 1>;
- interrupt-parent = <&mpic>;
- interrupts = <09 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- compatible = "85xx";
- device_type = "pci";
- };
+ /* IDSEL 0x10 */
+ 08000 0 0 1 &mpic 0 1
+ 08000 0 0 2 &mpic 1 1
+ 08000 0 0 3 &mpic 2 1
+ 08000 0 0 4 &mpic 3 1
- mpic: pic@40000 {
- clock-frequency = <0>;
+ /* IDSEL 0x11 */
+ 08800 0 0 1 &mpic 0 1
+ 08800 0 0 2 &mpic 1 1
+ 08800 0 0 3 &mpic 2 1
+ 08800 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 09000 0 0 1 &mpic 0 1
+ 09000 0 0 2 &mpic 1 1
+ 09000 0 0 3 &mpic 2 1
+ 09000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 09800 0 0 1 &mpic 1 1
+ 09800 0 0 2 &mpic 2 1
+ 09800 0 0 3 &mpic 3 1
+ 09800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0a000 0 0 1 &mpic 2 1
+ 0a000 0 0 2 &mpic 3 1
+ 0a000 0 0 3 &mpic 0 1
+ 0a000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0a800 0 0 1 &mpic 3 1
+ 0a800 0 0 2 &mpic 0 1
+ 0a800 0 0 3 &mpic 1 1
+ 0a800 0 0 4 &mpic 2 1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 19000 0 0 1 &mpic 0 1
+ 19000 0 0 2 &mpic 1 1
+ 19000 0 0 3 &mpic 2 1
+ 19000 0 0 4 &mpic 3 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ i8259@19000 {
interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
+ compatible = "chrp,iic";
+ interrupts = <1>;
+ interrupt-parent = <&pci1>;
};
};
+
+ pci@e0009000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic b 1
+ a800 0 0 2 &mpic b 1
+ a800 0 0 3 &mpic b 1
+ a800 0 0 4 &mpic b 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
};
git.openpandora.org / pandora-kernel.git / blobdiff