* any warranty of any kind, whether express or implied.
*/
+/dts-v1/;
+
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "amcc,canyonlands";
compatible = "amcc,canyonlands";
- dcr-parent = <&/cpus/cpu@0>;
+ dcr-parent = <&{/cpus/cpu@0}>;
aliases {
ethernet0 = &EMAC0;
cpu@0 {
device_type = "cpu";
model = "PowerPC,460EX";
- reg = <0>;
+ reg = <0x00000000>;
clock-frequency = <0>; /* Filled in by U-Boot */
timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <20>;
- d-cache-line-size = <20>;
- i-cache-size = <8000>;
- d-cache-size = <8000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
};
memory {
device_type = "memory";
- reg = <0 0 0>; /* Filled in by U-Boot */
+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <0>;
- dcr-reg = <0c0 009>;
+ dcr-reg = <0x0c0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <1>;
- dcr-reg = <0d0 009>;
+ dcr-reg = <0x0d0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
- interrupts = <1e 4 1f 4>; /* cascade */
+ interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <2>;
- dcr-reg = <0e0 009>;
+ dcr-reg = <0x0e0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
- interrupts = <a 4 b 4>; /* cascade */
+ interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <3>;
- dcr-reg = <0f0 009>;
+ dcr-reg = <0x0f0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
- interrupts = <10 4 11 4>; /* cascade */
+ interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
SDR0: sdr {
compatible = "ibm,sdr-460ex";
- dcr-reg = <00e 002>;
+ dcr-reg = <0x00e 0x002>;
};
CPR0: cpr {
compatible = "ibm,cpr-460ex";
- dcr-reg = <00c 002>;
+ dcr-reg = <0x00c 0x002>;
};
plb {
SDRAM0: sdram {
compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
- dcr-reg = <010 2>;
+ dcr-reg = <0x010 0x002>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
- dcr-reg = <180 62>;
+ dcr-reg = <0x180 0x062>;
num-tx-chans = <2>;
- num-rx-chans = <10>;
+ num-rx-chans = <16>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-parent = <&UIC2>;
- interrupts = < /*TXEOB*/ 6 4
- /*RXEOB*/ 7 4
- /*SERR*/ 3 4
- /*TXDE*/ 4 4
- /*RXDE*/ 5 4>;
+ interrupts = < /*TXEOB*/ 0x6 0x4
+ /*RXEOB*/ 0x7 0x4
+ /*SERR*/ 0x3 0x4
+ /*TXDE*/ 0x4 0x4
+ /*RXDE*/ 0x5 0x4>;
};
POB0: opb {
compatible = "ibm,opb-460ex", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <b0000000 4 b0000000 50000000>;
+ ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
clock-frequency = <0>; /* Filled in by U-Boot */
EBC0: ebc {
compatible = "ibm,ebc-460ex", "ibm,ebc";
- dcr-reg = <012 2>;
+ dcr-reg = <0x012 0x002>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by U-Boot */
- interrupts = <6 4>;
+ /* ranges property is supplied by U-Boot */
+ interrupts = <0x6 0x4>;
interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "amd,s29gl512n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0x00000000 0x00000000 0x04000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "kernel";
+ reg = <0x00000000 0x001e0000>;
+ };
+ partition@1e0000 {
+ label = "dtb";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@200000 {
+ label = "ramdisk";
+ reg = <0x00200000 0x01400000>;
+ };
+ partition@1600000 {
+ label = "jffs2";
+ reg = <0x01600000 0x00400000>;
+ };
+ partition@1a00000 {
+ label = "user";
+ reg = <0x01a00000 0x02560000>;
+ };
+ partition@3f60000 {
+ label = "env";
+ reg = <0x03f60000 0x00040000>;
+ };
+ partition@3fa0000 {
+ label = "u-boot";
+ reg = <0x03fa0000 0x00060000>;
+ };
+ };
};
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
- reg = <ef600300 8>;
- virtual-reg = <ef600300>;
+ reg = <0xef600300 0x00000008>;
+ virtual-reg = <0xef600300>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
- interrupts = <1 4>;
+ interrupts = <0x1 0x4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
- reg = <ef600400 8>;
- virtual-reg = <ef600400>;
+ reg = <0xef600400 0x00000008>;
+ virtual-reg = <0xef600400>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC0>;
- interrupts = <1 4>;
+ interrupts = <0x1 0x4>;
};
UART2: serial@ef600500 {
device_type = "serial";
compatible = "ns16550";
- reg = <ef600500 8>;
- virtual-reg = <ef600500>;
+ reg = <0xef600500 0x00000008>;
+ virtual-reg = <0xef600500>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
- interrupts = <1d 4>;
+ interrupts = <0x1d 0x4>;
};
UART3: serial@ef600600 {
device_type = "serial";
compatible = "ns16550";
- reg = <ef600600 8>;
- virtual-reg = <ef600600>;
+ reg = <0xef600600 0x00000008>;
+ virtual-reg = <0xef600600>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
- interrupts = <1e 4>;
+ interrupts = <0x1e 0x4>;
};
IIC0: i2c@ef600700 {
compatible = "ibm,iic-460ex", "ibm,iic";
- reg = <ef600700 14>;
+ reg = <0xef600700 0x00000014>;
interrupt-parent = <&UIC0>;
- interrupts = <2 4>;
+ interrupts = <0x2 0x4>;
};
IIC1: i2c@ef600800 {
compatible = "ibm,iic-460ex", "ibm,iic";
- reg = <ef600800 14>;
+ reg = <0xef600800 0x00000014>;
interrupt-parent = <&UIC0>;
- interrupts = <3 4>;
+ interrupts = <0x3 0x4>;
};
ZMII0: emac-zmii@ef600d00 {
compatible = "ibm,zmii-460ex", "ibm,zmii";
- reg = <ef600d00 c>;
+ reg = <0xef600d00 0x0000000c>;
};
RGMII0: emac-rgmii@ef601500 {
compatible = "ibm,rgmii-460ex", "ibm,rgmii";
- reg = <ef601500 8>;
+ reg = <0xef601500 0x00000008>;
has-mdio;
};
TAH0: emac-tah@ef601350 {
compatible = "ibm,tah-460ex", "ibm,tah";
- reg = <ef601350 30>;
+ reg = <0xef601350 0x00000030>;
};
TAH1: emac-tah@ef601450 {
compatible = "ibm,tah-460ex", "ibm,tah";
- reg = <ef601450 30>;
+ reg = <0xef601450 0x00000030>;
};
EMAC0: ethernet@ef600e00 {
device_type = "network";
- compatible = "ibm,emac-460ex", "ibm,emac4";
+ compatible = "ibm,emac-460ex", "ibm,emac4sync";
interrupt-parent = <&EMAC0>;
- interrupts = <0 1>;
+ interrupts = <0x0 0x1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = </*Status*/ 0 &UIC2 10 4
- /*Wake*/ 1 &UIC2 14 4>;
- reg = <ef600e00 70>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
+ /*Wake*/ 0x1 &UIC2 0x14 0x4>;
+ reg = <0xef600e00 0x000000c4>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
- max-frame-size = <2328>;
- rx-fifo-size = <1000>;
- tx-fifo-size = <800>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
phy-mode = "rgmii";
- phy-map = <00000000>;
+ phy-map = <0x00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <0>;
tah-device = <&TAH0>;
EMAC1: ethernet@ef600f00 {
device_type = "network";
- compatible = "ibm,emac-460ex", "ibm,emac4";
+ compatible = "ibm,emac-460ex", "ibm,emac4sync";
interrupt-parent = <&EMAC1>;
- interrupts = <0 1>;
+ interrupts = <0x0 0x1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = </*Status*/ 0 &UIC2 11 4
- /*Wake*/ 1 &UIC2 15 4>;
- reg = <ef600f00 70>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
+ /*Wake*/ 0x1 &UIC2 0x15 0x4>;
+ reg = <0xef600f00 0x000000c4>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <1>;
mal-rx-channel = <8>;
cell-index = <1>;
- max-frame-size = <2328>;
- rx-fifo-size = <1000>;
- tx-fifo-size = <800>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
phy-mode = "rgmii";
- phy-map = <00000000>;
+ phy-map = <0x00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <1>;
tah-device = <&TAH1>;
primary;
large-inbound-windows;
enable-msi-hole;
- reg = <c 0ec00000 8 /* Config space access */
- 0 0 0 /* no IACK cycles */
- c 0ed00000 4 /* Special cycles */
- c 0ec80000 100 /* Internal registers */
- c 0ec80100 fc>; /* Internal messaging registers */
+ reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
+ 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
+ 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
+ 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
+ 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
- ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
- 01000000 0 00000000 0000000c 08000000 0 00010000>;
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
+ 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
- dma-ranges = <42000000 0 0 0 0 0 80000000>;
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 0 to 0x3f */
- bus-range = <0 3f>;
+ bus-range = <0x0 0x3f>;
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
- interrupt-map-mask = <0000 0 0 0>;
- interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
};
PCIE0: pciex@d00000000 {
#address-cells = <3>;
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
primary;
- port = <0>; /* port number */
- reg = <d 00000000 20000000 /* Config space access */
- c 08010000 00001000>; /* Registers */
- dcr-reg = <100 020>;
- sdr-base = <300>;
+ port = <0x0>; /* port number */
+ reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
+ 0x0000000c 0x08010000 0x00001000>; /* Registers */
+ dcr-reg = <0x100 0x020>;
+ sdr-base = <0x300>;
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
- ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
- 01000000 0 00000000 0000000f 80000000 0 00010000>;
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
- dma-ranges = <42000000 0 0 0 0 0 80000000>;
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 40 to 0x7f */
- bus-range = <40 7f>;
+ bus-range = <0x40 0x7f>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
- interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
- 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
- 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
- 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
- 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
+ 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
};
PCIE1: pciex@d20000000 {
#address-cells = <3>;
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
primary;
- port = <1>; /* port number */
- reg = <d 20000000 20000000 /* Config space access */
- c 08011000 00001000>; /* Registers */
- dcr-reg = <120 020>;
- sdr-base = <340>;
+ port = <0x1>; /* port number */
+ reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
+ 0x0000000c 0x08011000 0x00001000>; /* Registers */
+ dcr-reg = <0x120 0x020>;
+ sdr-base = <0x340>;
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
- ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
- 01000000 0 00000000 0000000f 80010000 0 00010000>;
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
- dma-ranges = <42000000 0 0 0 0 0 80000000>;
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 80 to 0xbf */
- bus-range = <80 bf>;
+ bus-range = <0x80 0xbf>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
- interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
- 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
- 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
- 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
- 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
+ 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
};
};
};
git.openpandora.org / pandora-kernel.git / blobdiff