*
*/
-#include <linux/config.h>
+#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
#include <asm/uaccess.h>
/* #define DEBUG_UNALIGNED 1 */
#define DPRINTF(fmt, args...)
#endif
-#ifdef __LP64__
+#ifdef CONFIG_64BIT
#define RFMT "%016lx"
#else
#define RFMT "%08lx"
"\tldil L%%" #lbl ", %%r1\n" \
"\tldo R%%" #lbl "(%%r1), %%r1\n" \
"\tbv,n %%r0(%%r1)\n"
+/* If you use FIXUP_BRANCH, then you must list this clobber */
+#define FIXUP_BRANCH_CLOBBER "r1"
/* 1111 1100 0000 0000 0001 0011 1100 0000 */
#define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
"4: ldi -2, %1\n"
FIXUP_BRANCH(3b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,4b\n"
-" .dword 2b,4b\n"
-#else
-" .word 1b,4b\n"
-" .word 2b,4b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b, 4b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b, 4b)
: "=r" (val), "=r" (ret)
: "0" (val), "r" (saddr), "r" (regs->isr)
- : "r20" );
+ : "r20", FIXUP_BRANCH_CLOBBER );
DPRINTF("val = 0x" RFMT "\n", val);
"4: ldi -2, %1\n"
FIXUP_BRANCH(3b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,4b\n"
-" .dword 2b,4b\n"
-#else
-" .word 1b,4b\n"
-" .word 2b,4b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b, 4b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b, 4b)
: "=r" (val), "=r" (ret)
: "0" (val), "r" (saddr), "r" (regs->isr)
- : "r19", "r20" );
+ : "r19", "r20", FIXUP_BRANCH_CLOBBER );
DPRINTF("val = 0x" RFMT "\n", val);
regs->isr, regs->ior, toreg);
#ifdef CONFIG_PA20
-#ifndef __LP64__
+#ifndef CONFIG_64BIT
if (!flop)
return -1;
#endif
"4: ldi -2, %1\n"
FIXUP_BRANCH(3b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,4b\n"
-" .dword 2b,4b\n"
-#else
-" .word 1b,4b\n"
-" .word 2b,4b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
: "=r" (val), "=r" (ret)
: "0" (val), "r" (saddr), "r" (regs->isr)
- : "r19", "r20" );
+ : "r19", "r20", FIXUP_BRANCH_CLOBBER );
#else
{
unsigned long valh=0,vall=0;
"5: ldi -2, %2\n"
FIXUP_BRANCH(4b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,5b\n"
-" .dword 2b,5b\n"
-" .dword 3b,5b\n"
-#else
-" .word 1b,5b\n"
-" .word 2b,5b\n"
-" .word 3b,5b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b,5b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b,5b)
+ ASM_EXCEPTIONTABLE_ENTRY(3b,5b)
: "=r" (valh), "=r" (vall), "=r" (ret)
: "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr)
- : "r19", "r20" );
+ : "r19", "r20", FIXUP_BRANCH_CLOBBER );
val=((__u64)valh<<32)|(__u64)vall;
}
#endif
"4: ldi -2, %0\n"
FIXUP_BRANCH(3b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,4b\n"
-" .dword 2b,4b\n"
-#else
-" .word 1b,4b\n"
-" .word 2b,4b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
: "=r" (ret)
: "r" (val), "r" (regs->ior), "r" (regs->isr)
- : "r19" );
+ : "r19", FIXUP_BRANCH_CLOBBER );
return ret;
}
"4: ldi -2, %0\n"
FIXUP_BRANCH(3b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,4b\n"
-" .dword 2b,4b\n"
-#else
-" .word 1b,4b\n"
-" .word 2b,4b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
: "=r" (ret)
: "r" (val), "r" (regs->ior), "r" (regs->isr)
- : "r19", "r20", "r21", "r22", "r1" );
+ : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
return 0;
}
val, regs->isr, regs->ior);
#ifdef CONFIG_PA20
-#ifndef __LP64__
+#ifndef CONFIG_64BIT
if (!flop)
return -1;
#endif
"6: ldi -2, %0\n"
FIXUP_BRANCH(5b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,6b\n"
-" .dword 2b,6b\n"
-" .dword 3b,6b\n"
-" .dword 4b,6b\n"
-#else
-" .word 1b,6b\n"
-" .word 2b,6b\n"
-" .word 3b,6b\n"
-" .word 4b,6b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b,6b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b,6b)
+ ASM_EXCEPTIONTABLE_ENTRY(3b,6b)
+ ASM_EXCEPTIONTABLE_ENTRY(4b,6b)
: "=r" (ret)
: "r" (val), "r" (regs->ior), "r" (regs->isr)
- : "r19", "r20", "r21", "r22", "r1" );
+ : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
#else
{
unsigned long valh=(val>>32),vall=(val&0xffffffffl);
"7: ldi -2, %0\n"
FIXUP_BRANCH(6b)
" .previous\n"
-" .section __ex_table,\"aw\"\n"
-#ifdef __LP64__
-" .dword 1b,7b\n"
-" .dword 2b,7b\n"
-" .dword 3b,7b\n"
-" .dword 4b,7b\n"
-" .dword 5b,7b\n"
-#else
-" .word 1b,7b\n"
-" .word 2b,7b\n"
-" .word 3b,7b\n"
-" .word 4b,7b\n"
-" .word 5b,7b\n"
-#endif
-" .previous\n"
+ ASM_EXCEPTIONTABLE_ENTRY(1b,7b)
+ ASM_EXCEPTIONTABLE_ENTRY(2b,7b)
+ ASM_EXCEPTIONTABLE_ENTRY(3b,7b)
+ ASM_EXCEPTIONTABLE_ENTRY(4b,7b)
+ ASM_EXCEPTIONTABLE_ENTRY(5b,7b)
: "=r" (ret)
: "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
- : "r19", "r20", "r21", "r1" );
+ : "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER );
}
#endif