[MIPS] TXx9: Make single kernel can support multiple boards

[pandora-kernel.git] / arch / mips / txx9 / rbtx4938 / irq.c

diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index f498482..3971a06 100644 (file)
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -66,6 +66,8 @@ IRQ  Device
 */
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <asm/mipsregs.h>
+#include <asm/txx9/generic.h>
 #include <asm/txx9/rbtx4938.h>
 
 static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
@@ -80,26 +82,17 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
        .unmask = toshiba_rbtx4938_irq_ioc_enable,
 };
 
-int
-toshiba_rbtx4938_irq_nested(int sw_irq)
+static int toshiba_rbtx4938_irq_nested(int sw_irq)
 {
        u8 level3;
 
        level3 = readb(rbtx4938_imstat_addr);
        if (level3)
                /* must use fls so onboard ATA has priority */
-               sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
-
+               sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
        return sw_irq;
 }
 
-static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
-       .handler = no_action,
-       .flags = 0,
-       .mask = CPU_MASK_NONE,
-       .name = TOSHIBA_RBTX4938_IOC_NAME,
-};
-
 /**********************************************************************************/
 /* Functions for ioc                                                              */
 /**********************************************************************************/
@@ -108,13 +101,12 @@ toshiba_rbtx4938_irq_ioc_init(void)
 {
        int i;
 
-       for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
-            i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
+       for (i = RBTX4938_IRQ_IOC;
+            i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
                set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
                                         handle_level_irq);
 
-       setup_irq(RBTX4938_IRQ_IOCINT,
-                 &toshiba_rbtx4938_irq_ioc_action);
+       set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
 }
 
 static void
@@ -123,7 +115,7 @@ toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
        unsigned char v;
 
        v = readb(rbtx4938_imask_addr);
-       v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
+       v |= (1 << (irq - RBTX4938_IRQ_IOC));
        writeb(v, rbtx4938_imask_addr);
        mmiowb();
 }
@@ -134,15 +126,33 @@ toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
        unsigned char v;
 
        v = readb(rbtx4938_imask_addr);
-       v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
+       v &= ~(1 << (irq - RBTX4938_IRQ_IOC));
        writeb(v, rbtx4938_imask_addr);
        mmiowb();
 }
 
-void __init arch_init_irq(void)
+static int rbtx4938_irq_dispatch(int pending)
 {
-       extern void tx4938_irq_init(void);
+       int irq;
+
+       if (pending & STATUSF_IP7)
+               irq = MIPS_CPU_IRQ_BASE + 7;
+       else if (pending & STATUSF_IP2) {
+               irq = txx9_irq();
+               if (irq == RBTX4938_IRQ_IOCINT)
+                       irq = toshiba_rbtx4938_irq_nested(irq);
+       } else if (pending & STATUSF_IP1)
+               irq = MIPS_CPU_IRQ_BASE + 0;
+       else if (pending & STATUSF_IP0)
+               irq = MIPS_CPU_IRQ_BASE + 1;
+       else
+               irq = -1;
+       return irq;
+}
 
+void __init rbtx4938_irq_setup(void)
+{
+       txx9_irq_dispatch = rbtx4938_irq_dispatch;
        /* Now, interrupt control disabled, */
        /* all IRC interrupts are masked, */
        /* all IRC interrupt mode are Low Active. */