Pull cpuidle into release branch

[pandora-kernel.git] / arch / mips / sibyte / sb1250 / irq.c

diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 7659174..53780a1 100644 (file)
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -400,43 +400,27 @@ static void sb1250_kgdb_interrupt(void)
 
 #endif         /* CONFIG_KGDB */
 
-static inline void sb1250_timer_interrupt(void)
-{
-       int cpu = smp_processor_id();
-       int irq = K_INT_TIMER_0 + cpu;
-
-       irq_enter();
-       kstat_this_cpu.irqs[irq]++;
-
-       write_seqlock(&xtime_lock);
-
-       /* ACK interrupt */
-       ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
-                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-
-       /*
-        * call the generic timer interrupt handling
-        */
-       do_timer(1);
+extern void sb1250_mailbox_interrupt(void);
 
-       write_sequnlock(&xtime_lock);
+static inline void dispatch_ip2(void)
+{
+       unsigned int cpu = smp_processor_id();
+       unsigned long long mask;
 
        /*
-        * In UP mode, we call local_timer_interrupt() to do profiling
-        * and process accouting.
-        *
-        * In SMP mode, local_timer_interrupt() is invoked by appropriate
-        * low-level local timer interrupt handler.
+        * Default...we've hit an IP[2] interrupt, which means we've got to
+        * check the 1250 interrupt registers to figure out what to do.  Need
+        * to detect which CPU we're on, now that smp_affinity is supported.
         */
-       local_timer_interrupt(irq);
-
-       irq_exit();
+       mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
+                                 R_IMR_INTERRUPT_STATUS_BASE)));
+       if (mask)
+               do_IRQ(fls64(mask) - 1);
 }
 
-extern void sb1250_mailbox_interrupt(void);
-
 asmlinkage void plat_irq_dispatch(void)
 {
+       unsigned int cpu = smp_processor_id();
        unsigned int pending;
 
        /*
@@ -454,7 +438,7 @@ asmlinkage void plat_irq_dispatch(void)
        if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
        else if (pending & CAUSEF_IP4)
-               sb1250_timer_interrupt();
+               do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
 
 #ifdef CONFIG_SMP
        else if (pending & CAUSEF_IP3)
@@ -466,21 +450,8 @@ asmlinkage void plat_irq_dispatch(void)
                sb1250_kgdb_interrupt();
 #endif
 
-       else if (pending & CAUSEF_IP2) {
-               unsigned long long mask;
-
-               /*
-                * Default...we've hit an IP[2] interrupt, which means we've
-                * got to check the 1250 interrupt registers to figure out what
-                * to do.  Need to detect which CPU we're on, now that
-                * smp_affinity is supported.
-                */
-               mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
-                                             R_IMR_INTERRUPT_STATUS_BASE)));
-               if (mask)
-                       do_IRQ(fls64(mask) - 1);
-               else
-                       spurious_interrupt();
-       } else
+       else if (pending & CAUSEF_IP2)
+               dispatch_ip2();
+       else
                spurious_interrupt();
 }