Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux...

[pandora-kernel.git] / arch / mips / momentum / ocelot_c / irq.c

diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index a5764bc..9d44ae1 100644 (file)
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -48,18 +48,44 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 
-extern asmlinkage void ocelot_handle_int(void);
 extern void uart_irq_init(void);
 extern void cpci_irq_init(void);
 
 static struct irqaction cascade_fpga = {
-       no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
+       no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
 };
 
 static struct irqaction cascade_mv64340 = {
-       no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
+       no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
 };
 
+extern void ll_uart_irq(struct pt_regs *regs);
+extern void ll_cpci_irq(struct pt_regs *regs);
+
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+       unsigned int pending = read_c0_cause() & read_c0_status();
+
+       if (pending & STATUSF_IP0)
+               do_IRQ(0, regs);
+       else if (pending & STATUSF_IP1)
+               do_IRQ(1, regs);
+       else if (pending & STATUSF_IP2)
+               do_IRQ(2, regs);
+       else if (pending & STATUSF_IP3)
+               ll_uart_irq(regs);
+       else if (pending & STATUSF_IP4)
+               do_IRQ(4, regs);
+       else if (pending & STATUSF_IP5)
+               ll_cpci_irq(regs);
+       else if (pending & STATUSF_IP6)
+               ll_mv64340_irq(regs);
+       else if (pending & STATUSF_IP7)
+               do_IRQ(7, regs);
+       else
+               spurious_interrupt(regs);
+}
+
 void __init arch_init_irq(void)
 {
        /*
@@ -68,8 +94,6 @@ void __init arch_init_irq(void)
         */
        clear_c0_status(ST0_IM);
 
-       /* Sets the first-level interrupt dispatcher. */
-       set_except_vector(0, ocelot_handle_int);
        mips_cpu_irq_init(0);
 
        /* set up the cascading interrupts */