value = OCELOT_FPGA_READ(INTMASK);
}
-/*
- * End IRQ processing
- */
-static void end_cpci_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- unmask_cpci_irq(irq);
-}
-
/*
* Interrupt handler for interrupts coming from the FPGA chip.
* It could be built in ethernet ports etc...
}
struct irq_chip cpci_irq_type = {
- .typename = "CPCI/FPGA",
+ .name = "CPCI/FPGA",
.ack = mask_cpci_irq,
.mask = mask_cpci_irq,
.mask_ack = mask_cpci_irq,
.unmask = unmask_cpci_irq,
- .end = end_cpci_irq,
};
void cpci_irq_init(void)
int i;
for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
- set_irq_chip(i, &cpci_irq_type);
+ set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
}