Merge branch 'vhost-net-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mst...

[pandora-kernel.git] / arch / mips / mm / sc-mips.c

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8..505feca 100644 (file)
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -57,6 +57,34 @@ static struct bcache_ops mips_sc_ops = {
        .bc_inv = mips_sc_inv
 };
 
+/*
+ * Check if the L2 cache controller is activated on a particular platform.
+ * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
+ * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
+ * cache being disabled.  However there is no guarantee for this to be
+ * true on all platforms.  In an act of stupidity the spec defined bits
+ * 12..15 as implementation defined so below function will eventually have
+ * to be replaced by a platform specific probe.
+ */
+static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
+{
+       /* Check the bypass bit (L2B) */
+       switch (c->cputype) {
+       case CPU_34K:
+       case CPU_74K:
+       case CPU_1004K:
+       case CPU_BMIPS5000:
+               if (config2 & (1 << 12))
+                       return 0;
+       }
+
+       tmp = (config2 >> 4) & 0x0f;
+       if (0 < tmp && tmp <= 7)
+               c->scache.linesz = 2 << tmp;
+       else
+               return 0;
+}
+
 static inline int __init mips_sc_probe(void)
 {
        struct cpuinfo_mips *c = &current_cpu_data;
@@ -79,10 +107,8 @@ static inline int __init mips_sc_probe(void)
                return 0;
 
        config2 = read_c0_config2();
-       tmp = (config2 >> 4) & 0x0f;
-       if (0 < tmp && tmp <= 7)
-               c->scache.linesz = 2 << tmp;
-       else
+
+       if (!mips_sc_is_activated(c))
                return 0;
 
        tmp = (config2 >> 8) & 0x0f;