Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6

[pandora-kernel.git] / arch / mips / mm / c-r4k.c

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6e99665..58d9075 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -618,15 +618,35 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
        if (cpu_has_inclusive_pcaches) {
                if (size >= scache_size)
                        r4k_blast_scache();
-               else
+               else {
+                       unsigned long lsize = cpu_scache_line_size();
+                       unsigned long almask = ~(lsize - 1);
+
+                       /*
+                        * There is no clearly documented alignment requirement
+                        * for the cache instruction on MIPS processors and
+                        * some processors, among them the RM5200 and RM7000
+                        * QED processors will throw an address error for cache
+                        * hit ops with insufficient alignment.  Solved by
+                        * aligning the address to cache line size.
+                        */
+                       cache_op(Hit_Writeback_Inv_SD, addr & almask);
+                       cache_op(Hit_Writeback_Inv_SD,
+                                (addr + size - 1) & almask);
                        blast_inv_scache_range(addr, addr + size);
+               }
                return;
        }
 
        if (cpu_has_safe_index_cacheops && size >= dcache_size) {
                r4k_blast_dcache();
        } else {
+               unsigned long lsize = cpu_dcache_line_size();
+               unsigned long almask = ~(lsize - 1);
+
                R4600_HIT_CACHEOP_WAR_IMPL;
+               cache_op(Hit_Writeback_Inv_D, addr & almask);
+               cache_op(Hit_Writeback_Inv_D, (addr + size - 1)  & almask);
                blast_inv_dcache_range(addr, addr + size);
        }
 
@@ -760,7 +780,7 @@ static void __cpuinit probe_pcache(void)
                c->dcache.ways = 2;
                c->dcache.waybit = 0;
 
-               c->options |= MIPS_CPU_CACHE_CDEX_P;
+               c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
                break;
 
        case CPU_TX49XX:
@@ -1006,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
                c->icache.flags |= MIPS_CACHE_VTAG;
                break;
 
-       case CPU_AU1000:
-       case CPU_AU1500:
-       case CPU_AU1100:
-       case CPU_AU1550:
-       case CPU_AU1200:
-       case CPU_AU1210:
-       case CPU_AU1250:
+       case CPU_ALCHEMY:
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
                break;
        }
@@ -1224,7 +1238,7 @@ void au1x00_fixup_config_od(void)
        /*
         * Au1100 errata actually keeps silence about this bit, so we set it
         * just in case for those revisions that require it to be set according
-        * to arch/mips/au1000/common/cputable.c
+        * to the (now gone) cpu table.
         */
        case 0x02030200: /* Au1100 AB */
        case 0x02030201: /* Au1100 BA */
@@ -1294,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
                break;
        /*
         * We need to catch the early Alchemy SOCs with
-        * the write-only co_config.od bit and set it back to one...
+        * the write-only co_config.od bit and set it back to one on:
+        * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
         */
-       case CPU_AU1000: /* rev. DA, HA, HB */
-       case CPU_AU1100: /* rev. AB, BA, BC ?? */
-       case CPU_AU1500: /* rev. AB */
+       case CPU_ALCHEMY:
                au1x00_fixup_config_od();
                break;