[IA64] relax per-cpu TLB requirement to DTC

[pandora-kernel.git] / arch / mips / mips-boards / malta / malta_smp.c

diff --git a/arch/mips/mips-boards/malta/malta_smp.c b/arch/mips/mips-boards/malta/malta_smp.c
index 6c6c8ee..cf96717 100644 (file)
--- a/arch/mips/mips-boards/malta/malta_smp.c
+++ b/arch/mips/mips-boards/malta/malta_smp.c
@@ -33,25 +33,6 @@ void core_send_ipi(int cpu, unsigned int action)
 #endif /* CONFIG_MIPS_MT_SMTC */
 }
 
-/*
- * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
- */
-
-void __init prom_build_cpu_map(void)
-{
-       int nextslot;
-
-       /*
-        * As of November, 2004, MIPSsim only simulates one core
-        * at a time.  However, that core may be a MIPS MT core
-        * with multiple virtual processors and thread contexts.
-        */
-
-       if (read_c0_config3() & (1<<2)) {
-               nextslot = mipsmt_build_cpu_map(1);
-       }
-}
-
 /*
  * Platform "CPU" startup hook
  */