Pull novell-bugzilla-156426 into release branch

[pandora-kernel.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5e1b08b..8c2c359 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2,8 +2,8 @@
  * Processor capabilities determination functions.
  *
  * Copyright (C) xxxx  the Anonymous
+ * Copyright (C) 1994 - 2006 Ralf Baechle
  * Copyright (C) 2003, 2004  Maciej W. Rozycki
- * Copyright (C) 1994 - 2003 Ralf Baechle
  * Copyright (C) 2001, 2004  MIPS Inc.
  *
  * This program is free software; you can redistribute it and/or
@@ -121,6 +121,7 @@ static inline void check_wait(void)
        case CPU_24K:
        case CPU_25KF:
        case CPU_34K:
+       case CPU_74K:
        case CPU_PR4450:
                cpu_wait = r4k_wait;
                printk(" available.\n");
@@ -291,7 +292,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 * for documentation.  Commented out because it shares
                 * it's c0_prid id number with the TX3900.
                 */
-               c->cputype = CPU_R4650;
+               c->cputype = CPU_R4650;
                c->isa_level = MIPS_CPU_ISA_III;
                c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
                c->tlbsize = 48;
@@ -432,9 +433,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                             MIPS_CPU_LLSC;
                c->tlbsize = 64;
                break;
+       case PRID_IMP_R14000:
+               c->cputype = CPU_R14000;
+               c->isa_level = MIPS_CPU_ISA_IV;
+               c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
+                            MIPS_CPU_FPU | MIPS_CPU_32FPR |
+                            MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
+                            MIPS_CPU_LLSC;
+               c->tlbsize = 64;
+               break;
        }
 }
 
+static char unknown_isa[] __initdata = KERN_ERR \
+       "Unsupported ISA type, c0.config0: %d.";
+
 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 {
        unsigned int config0;
@@ -447,16 +460,37 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
        isa = (config0 & MIPS_CONF_AT) >> 13;
        switch (isa) {
        case 0:
-               c->isa_level = MIPS_CPU_ISA_M32;
+               switch ((config0 >> 10) & 7) {
+               case 0:
+                       c->isa_level = MIPS_CPU_ISA_M32R1;
+                       break;
+               case 1:
+                       c->isa_level = MIPS_CPU_ISA_M32R2;
+                       break;
+               default:
+                       goto unknown;
+               }
                break;
        case 2:
-               c->isa_level = MIPS_CPU_ISA_M64;
+               switch ((config0 >> 10) & 7) {
+               case 0:
+                       c->isa_level = MIPS_CPU_ISA_M64R1;
+                       break;
+               case 1:
+                       c->isa_level = MIPS_CPU_ISA_M64R2;
+                       break;
+               default:
+                       goto unknown;
+               }
                break;
        default:
-               panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
+               goto unknown;
        }
 
        return config0 & MIPS_CONF_M;
+
+unknown:
+       panic(unknown_isa, config0);
 }
 
 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
@@ -568,7 +602,9 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                break;
        case PRID_IMP_34K:
                c->cputype = CPU_34K;
-               c->isa_level = MIPS_CPU_ISA_M32;
+               break;
+       case PRID_IMP_74K:
+               c->cputype = CPU_74K;
                break;
        }
 }
@@ -581,7 +617,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
        case PRID_IMP_AU1_REV2:
                switch ((c->processor_id >> 24) & 0xff) {
                case 0:
-                       c->cputype = CPU_AU1000;
+                       c->cputype = CPU_AU1000;
                        break;
                case 1:
                        c->cputype = CPU_AU1500;
@@ -618,10 +654,9 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_SB1:
                c->cputype = CPU_SB1;
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
                /* FPU in pass1 is known to have issues. */
-               c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
-#endif
+               if ((c->processor_id & 0xff) < 0x02)
+                       c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
                break;
        case PRID_IMP_SB1A:
                c->cputype = CPU_SB1A;
@@ -647,7 +682,7 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c)
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_PR4450:
                c->cputype = CPU_PR4450;
-               c->isa_level = MIPS_CPU_ISA_M32;
+               c->isa_level = MIPS_CPU_ISA_M32R1;
                break;
        default:
                panic("Unknown Philips Core!"); /* REVISIT: die? */
@@ -683,15 +718,17 @@ __init void cpu_probe(void)
                break;
        case PRID_COMP_PHILIPS:
                cpu_probe_philips(c);
-               break;
+               break;
        default:
                c->cputype = CPU_UNKNOWN;
        }
        if (c->options & MIPS_CPU_FPU) {
                c->fpu_id = cpu_get_fpu_id();
 
-               if (c->isa_level == MIPS_CPU_ISA_M32 ||
-                   c->isa_level == MIPS_CPU_ISA_M64) {
+               if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+                   c->isa_level == MIPS_CPU_ISA_M32R2 ||
+                   c->isa_level == MIPS_CPU_ISA_M64R1 ||
+                   c->isa_level == MIPS_CPU_ISA_M64R2) {
                        if (c->fpu_id & MIPS_FPIR_3D)
                                c->ases |= MIPS_ASE_MIPS3D;
                }