MIPS: Alchemy: more base address cleanup

[pandora-kernel.git] / arch / mips / include / asm / mach-au1x00 / au1xxx_psc.h

diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 892b7f1..8e2fa67 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -33,19 +33,6 @@
 #ifndef _AU1000_PSC_H_
 #define _AU1000_PSC_H_
 
-/* The PSC base addresses.  */
-#ifdef CONFIG_SOC_AU1550
-#define PSC0_BASE_ADDR         0xb1a00000
-#define PSC1_BASE_ADDR         0xb1b00000
-#define PSC2_BASE_ADDR         0xb0a00000
-#define PSC3_BASE_ADDR         0xb0b00000
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-#define PSC0_BASE_ADDR         0xb1a00000
-#define PSC1_BASE_ADDR         0xb1b00000
-#endif
-
 /*
  * The PSC select and control registers are common to all protocols.
  */
@@ -80,19 +67,6 @@
 #define PSC_AC97GPO_OFFSET     0x00000028
 #define PSC_AC97GPI_OFFSET     0x0000002c
 
-#define AC97_PSC_SEL           (AC97_PSC_BASE + PSC_SEL_OFFSET)
-#define AC97_PSC_CTRL          (AC97_PSC_BASE + PSC_CTRL_OFFSET)
-#define PSC_AC97CFG            (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
-#define PSC_AC97MSK            (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
-#define PSC_AC97PCR            (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
-#define PSC_AC97STAT           (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
-#define PSC_AC97EVNT           (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
-#define PSC_AC97TXRX           (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
-#define PSC_AC97CDC            (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
-#define PSC_AC97RST            (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
-#define PSC_AC97GPO            (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
-#define PSC_AC97GPI            (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
-
 /* AC97 Config Register. */
 #define PSC_AC97CFG_RT_MASK    (3 << 30)
 #define PSC_AC97CFG_RT_FIFO1   (0 << 30)