return 0;
}
+#define ALCHEMY_CPU_UNKNOWN -1
+#define ALCHEMY_CPU_AU1000 0
+#define ALCHEMY_CPU_AU1500 1
+#define ALCHEMY_CPU_AU1100 2
+#define ALCHEMY_CPU_AU1550 3
+#define ALCHEMY_CPU_AU1200 4
+
+static inline int alchemy_get_cputype(void)
+{
+ switch (read_c0_prid() & 0xffff0000) {
+ case 0x00030000:
+ return ALCHEMY_CPU_AU1000;
+ break;
+ case 0x01030000:
+ return ALCHEMY_CPU_AU1500;
+ break;
+ case 0x02030000:
+ return ALCHEMY_CPU_AU1100;
+ break;
+ case 0x03030000:
+ return ALCHEMY_CPU_AU1550;
+ break;
+ case 0x04030000:
+ case 0x05030000:
+ return ALCHEMY_CPU_AU1200;
+ break;
+ }
+
+ return ALCHEMY_CPU_UNKNOWN;
+}
+
+static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
+ int timeout, i;
+
+ /* check LSR TX_EMPTY bit */
+ timeout = 0xffffff;
+ do {
+ if (__raw_readl(base + 0x1c) & 0x20)
+ break;
+ /* slow down */
+ for (i = 10000; i; i--)
+ asm volatile ("nop");
+ } while (--timeout);
+
+ __raw_writel(c, base + 0x04); /* tx */
+ wmb();
+}
+
/* arch/mips/au1000/common/clocks.c */
extern void set_au1x00_speed(unsigned int new_freq);
extern unsigned int get_au1x00_speed(void);
/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
void au1xxx_save_and_sleep(void);
void au_sleep(void);
-void save_au1xxx_intctl(void);
-void restore_au1xxx_intctl(void);
-/*
- * Every board describes its IRQ mapping with this table.
- */
-struct au1xxx_irqmap {
- int im_irq;
- int im_type;
- int im_request;
+
+/* SOC Interrupt numbers */
+
+#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
+#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
+#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
+#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
+#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
+
+enum soc_au1000_ints {
+ AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
+ AU1000_UART0_INT = AU1000_FIRST_INT,
+ AU1000_UART1_INT,
+ AU1000_UART2_INT,
+ AU1000_UART3_INT,
+ AU1000_SSI0_INT,
+ AU1000_SSI1_INT,
+ AU1000_DMA_INT_BASE,
+
+ AU1000_TOY_INT = AU1000_FIRST_INT + 14,
+ AU1000_TOY_MATCH0_INT,
+ AU1000_TOY_MATCH1_INT,
+ AU1000_TOY_MATCH2_INT,
+ AU1000_RTC_INT,
+ AU1000_RTC_MATCH0_INT,
+ AU1000_RTC_MATCH1_INT,
+ AU1000_RTC_MATCH2_INT,
+ AU1000_IRDA_TX_INT,
+ AU1000_IRDA_RX_INT,
+ AU1000_USB_DEV_REQ_INT,
+ AU1000_USB_DEV_SUS_INT,
+ AU1000_USB_HOST_INT,
+ AU1000_ACSYNC_INT,
+ AU1000_MAC0_DMA_INT,
+ AU1000_MAC1_DMA_INT,
+ AU1000_I2S_UO_INT,
+ AU1000_AC97C_INT,
+ AU1000_GPIO0_INT,
+ AU1000_GPIO1_INT,
+ AU1000_GPIO2_INT,
+ AU1000_GPIO3_INT,
+ AU1000_GPIO4_INT,
+ AU1000_GPIO5_INT,
+ AU1000_GPIO6_INT,
+ AU1000_GPIO7_INT,
+ AU1000_GPIO8_INT,
+ AU1000_GPIO9_INT,
+ AU1000_GPIO10_INT,
+ AU1000_GPIO11_INT,
+ AU1000_GPIO12_INT,
+ AU1000_GPIO13_INT,
+ AU1000_GPIO14_INT,
+ AU1000_GPIO15_INT,
+ AU1000_GPIO16_INT,
+ AU1000_GPIO17_INT,
+ AU1000_GPIO18_INT,
+ AU1000_GPIO19_INT,
+ AU1000_GPIO20_INT,
+ AU1000_GPIO21_INT,
+ AU1000_GPIO22_INT,
+ AU1000_GPIO23_INT,
+ AU1000_GPIO24_INT,
+ AU1000_GPIO25_INT,
+ AU1000_GPIO26_INT,
+ AU1000_GPIO27_INT,
+ AU1000_GPIO28_INT,
+ AU1000_GPIO29_INT,
+ AU1000_GPIO30_INT,
+ AU1000_GPIO31_INT,
+};
+
+enum soc_au1100_ints {
+ AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
+ AU1100_UART0_INT = AU1100_FIRST_INT,
+ AU1100_UART1_INT,
+ AU1100_SD_INT,
+ AU1100_UART3_INT,
+ AU1100_SSI0_INT,
+ AU1100_SSI1_INT,
+ AU1100_DMA_INT_BASE,
+
+ AU1100_TOY_INT = AU1100_FIRST_INT + 14,
+ AU1100_TOY_MATCH0_INT,
+ AU1100_TOY_MATCH1_INT,
+ AU1100_TOY_MATCH2_INT,
+ AU1100_RTC_INT,
+ AU1100_RTC_MATCH0_INT,
+ AU1100_RTC_MATCH1_INT,
+ AU1100_RTC_MATCH2_INT,
+ AU1100_IRDA_TX_INT,
+ AU1100_IRDA_RX_INT,
+ AU1100_USB_DEV_REQ_INT,
+ AU1100_USB_DEV_SUS_INT,
+ AU1100_USB_HOST_INT,
+ AU1100_ACSYNC_INT,
+ AU1100_MAC0_DMA_INT,
+ AU1100_GPIO208_215_INT,
+ AU1100_LCD_INT,
+ AU1100_AC97C_INT,
+ AU1100_GPIO0_INT,
+ AU1100_GPIO1_INT,
+ AU1100_GPIO2_INT,
+ AU1100_GPIO3_INT,
+ AU1100_GPIO4_INT,
+ AU1100_GPIO5_INT,
+ AU1100_GPIO6_INT,
+ AU1100_GPIO7_INT,
+ AU1100_GPIO8_INT,
+ AU1100_GPIO9_INT,
+ AU1100_GPIO10_INT,
+ AU1100_GPIO11_INT,
+ AU1100_GPIO12_INT,
+ AU1100_GPIO13_INT,
+ AU1100_GPIO14_INT,
+ AU1100_GPIO15_INT,
+ AU1100_GPIO16_INT,
+ AU1100_GPIO17_INT,
+ AU1100_GPIO18_INT,
+ AU1100_GPIO19_INT,
+ AU1100_GPIO20_INT,
+ AU1100_GPIO21_INT,
+ AU1100_GPIO22_INT,
+ AU1100_GPIO23_INT,
+ AU1100_GPIO24_INT,
+ AU1100_GPIO25_INT,
+ AU1100_GPIO26_INT,
+ AU1100_GPIO27_INT,
+ AU1100_GPIO28_INT,
+ AU1100_GPIO29_INT,
+ AU1100_GPIO30_INT,
+ AU1100_GPIO31_INT,
+};
+
+enum soc_au1500_ints {
+ AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
+ AU1500_UART0_INT = AU1500_FIRST_INT,
+ AU1500_PCI_INTA,
+ AU1500_PCI_INTB,
+ AU1500_UART3_INT,
+ AU1500_PCI_INTC,
+ AU1500_PCI_INTD,
+ AU1500_DMA_INT_BASE,
+
+ AU1500_TOY_INT = AU1500_FIRST_INT + 14,
+ AU1500_TOY_MATCH0_INT,
+ AU1500_TOY_MATCH1_INT,
+ AU1500_TOY_MATCH2_INT,
+ AU1500_RTC_INT,
+ AU1500_RTC_MATCH0_INT,
+ AU1500_RTC_MATCH1_INT,
+ AU1500_RTC_MATCH2_INT,
+ AU1500_PCI_ERR_INT,
+ AU1500_RESERVED_INT,
+ AU1500_USB_DEV_REQ_INT,
+ AU1500_USB_DEV_SUS_INT,
+ AU1500_USB_HOST_INT,
+ AU1500_ACSYNC_INT,
+ AU1500_MAC0_DMA_INT,
+ AU1500_MAC1_DMA_INT,
+ AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
+ AU1500_GPIO0_INT,
+ AU1500_GPIO1_INT,
+ AU1500_GPIO2_INT,
+ AU1500_GPIO3_INT,
+ AU1500_GPIO4_INT,
+ AU1500_GPIO5_INT,
+ AU1500_GPIO6_INT,
+ AU1500_GPIO7_INT,
+ AU1500_GPIO8_INT,
+ AU1500_GPIO9_INT,
+ AU1500_GPIO10_INT,
+ AU1500_GPIO11_INT,
+ AU1500_GPIO12_INT,
+ AU1500_GPIO13_INT,
+ AU1500_GPIO14_INT,
+ AU1500_GPIO15_INT,
+ AU1500_GPIO200_INT,
+ AU1500_GPIO201_INT,
+ AU1500_GPIO202_INT,
+ AU1500_GPIO203_INT,
+ AU1500_GPIO20_INT,
+ AU1500_GPIO204_INT,
+ AU1500_GPIO205_INT,
+ AU1500_GPIO23_INT,
+ AU1500_GPIO24_INT,
+ AU1500_GPIO25_INT,
+ AU1500_GPIO26_INT,
+ AU1500_GPIO27_INT,
+ AU1500_GPIO28_INT,
+ AU1500_GPIO206_INT,
+ AU1500_GPIO207_INT,
+ AU1500_GPIO208_215_INT,
};
-/* core calls this function to let boards initialize other IRQ sources */
-void board_init_irq(void);
+enum soc_au1550_ints {
+ AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
+ AU1550_UART0_INT = AU1550_FIRST_INT,
+ AU1550_PCI_INTA,
+ AU1550_PCI_INTB,
+ AU1550_DDMA_INT,
+ AU1550_CRYPTO_INT,
+ AU1550_PCI_INTC,
+ AU1550_PCI_INTD,
+ AU1550_PCI_RST_INT,
+ AU1550_UART1_INT,
+ AU1550_UART3_INT,
+ AU1550_PSC0_INT,
+ AU1550_PSC1_INT,
+ AU1550_PSC2_INT,
+ AU1550_PSC3_INT,
+ AU1550_TOY_INT,
+ AU1550_TOY_MATCH0_INT,
+ AU1550_TOY_MATCH1_INT,
+ AU1550_TOY_MATCH2_INT,
+ AU1550_RTC_INT,
+ AU1550_RTC_MATCH0_INT,
+ AU1550_RTC_MATCH1_INT,
+ AU1550_RTC_MATCH2_INT,
+
+ AU1550_NAND_INT = AU1550_FIRST_INT + 23,
+ AU1550_USB_DEV_REQ_INT,
+ AU1550_USB_DEV_SUS_INT,
+ AU1550_USB_HOST_INT,
+ AU1550_MAC0_DMA_INT,
+ AU1550_MAC1_DMA_INT,
+ AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
+ AU1550_GPIO1_INT,
+ AU1550_GPIO2_INT,
+ AU1550_GPIO3_INT,
+ AU1550_GPIO4_INT,
+ AU1550_GPIO5_INT,
+ AU1550_GPIO6_INT,
+ AU1550_GPIO7_INT,
+ AU1550_GPIO8_INT,
+ AU1550_GPIO9_INT,
+ AU1550_GPIO10_INT,
+ AU1550_GPIO11_INT,
+ AU1550_GPIO12_INT,
+ AU1550_GPIO13_INT,
+ AU1550_GPIO14_INT,
+ AU1550_GPIO15_INT,
+ AU1550_GPIO200_INT,
+ AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
+ AU1550_GPIO16_INT,
+ AU1550_GPIO17_INT,
+ AU1550_GPIO20_INT,
+ AU1550_GPIO21_INT,
+ AU1550_GPIO22_INT,
+ AU1550_GPIO23_INT,
+ AU1550_GPIO24_INT,
+ AU1550_GPIO25_INT,
+ AU1550_GPIO26_INT,
+ AU1550_GPIO27_INT,
+ AU1550_GPIO28_INT,
+ AU1550_GPIO206_INT,
+ AU1550_GPIO207_INT,
+ AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
+};
-/* boards call this to register additional (GPIO) interrupts */
-void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
+enum soc_au1200_ints {
+ AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
+ AU1200_UART0_INT = AU1200_FIRST_INT,
+ AU1200_SWT_INT,
+ AU1200_SD_INT,
+ AU1200_DDMA_INT,
+ AU1200_MAE_BE_INT,
+ AU1200_GPIO200_INT,
+ AU1200_GPIO201_INT,
+ AU1200_GPIO202_INT,
+ AU1200_UART1_INT,
+ AU1200_MAE_FE_INT,
+ AU1200_PSC0_INT,
+ AU1200_PSC1_INT,
+ AU1200_AES_INT,
+ AU1200_CAMERA_INT,
+ AU1200_TOY_INT,
+ AU1200_TOY_MATCH0_INT,
+ AU1200_TOY_MATCH1_INT,
+ AU1200_TOY_MATCH2_INT,
+ AU1200_RTC_INT,
+ AU1200_RTC_MATCH0_INT,
+ AU1200_RTC_MATCH1_INT,
+ AU1200_RTC_MATCH2_INT,
+ AU1200_GPIO203_INT,
+ AU1200_NAND_INT,
+ AU1200_GPIO204_INT,
+ AU1200_GPIO205_INT,
+ AU1200_GPIO206_INT,
+ AU1200_GPIO207_INT,
+ AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
+ AU1200_USB_INT,
+ AU1200_LCD_INT,
+ AU1200_MAE_BOTH_INT,
+ AU1200_GPIO0_INT,
+ AU1200_GPIO1_INT,
+ AU1200_GPIO2_INT,
+ AU1200_GPIO3_INT,
+ AU1200_GPIO4_INT,
+ AU1200_GPIO5_INT,
+ AU1200_GPIO6_INT,
+ AU1200_GPIO7_INT,
+ AU1200_GPIO8_INT,
+ AU1200_GPIO9_INT,
+ AU1200_GPIO10_INT,
+ AU1200_GPIO11_INT,
+ AU1200_GPIO12_INT,
+ AU1200_GPIO13_INT,
+ AU1200_GPIO14_INT,
+ AU1200_GPIO15_INT,
+ AU1200_GPIO16_INT,
+ AU1200_GPIO17_INT,
+ AU1200_GPIO18_INT,
+ AU1200_GPIO19_INT,
+ AU1200_GPIO20_INT,
+ AU1200_GPIO21_INT,
+ AU1200_GPIO22_INT,
+ AU1200_GPIO23_INT,
+ AU1200_GPIO24_INT,
+ AU1200_GPIO25_INT,
+ AU1200_GPIO26_INT,
+ AU1200_GPIO27_INT,
+ AU1200_GPIO28_INT,
+ AU1200_GPIO29_INT,
+ AU1200_GPIO30_INT,
+ AU1200_GPIO31_INT,
+};
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#define MEM_STNAND_DATA 0x20
#endif
+
+/* Interrupt Controller register offsets */
+#define IC_CFG0RD 0x40
+#define IC_CFG0SET 0x40
+#define IC_CFG0CLR 0x44
+#define IC_CFG1RD 0x48
+#define IC_CFG1SET 0x48
+#define IC_CFG1CLR 0x4C
+#define IC_CFG2RD 0x50
+#define IC_CFG2SET 0x50
+#define IC_CFG2CLR 0x54
+#define IC_REQ0INT 0x54
+#define IC_SRCRD 0x58
+#define IC_SRCSET 0x58
+#define IC_SRCCLR 0x5C
+#define IC_REQ1INT 0x5C
+#define IC_ASSIGNRD 0x60
+#define IC_ASSIGNSET 0x60
+#define IC_ASSIGNCLR 0x64
+#define IC_WAKERD 0x68
+#define IC_WAKESET 0x68
+#define IC_WAKECLR 0x6C
+#define IC_MASKRD 0x70
+#define IC_MASKSET 0x70
+#define IC_MASKCLR 0x74
+#define IC_RISINGRD 0x78
+#define IC_RISINGCLR 0x78
+#define IC_FALLINGRD 0x7C
+#define IC_FALLINGCLR 0x7C
+#define IC_TESTBIT 0x80
+
+
/* Interrupt Controller 0 */
#define IC0_CFG0RD 0xB0400040
#define IC0_CFG0SET 0xB0400040
#define IC1_TESTBIT 0xB1800080
-/* Interrupt Numbers */
+
/* Au1000 */
#ifdef CONFIG_SOC_AU1000
-enum soc_au1000_ints {
- AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
- AU1000_UART0_INT = AU1000_FIRST_INT,
- AU1000_UART1_INT, /* au1000 */
- AU1000_UART2_INT, /* au1000 */
- AU1000_UART3_INT,
- AU1000_SSI0_INT, /* au1000 */
- AU1000_SSI1_INT, /* au1000 */
- AU1000_DMA_INT_BASE,
-
- AU1000_TOY_INT = AU1000_FIRST_INT + 14,
- AU1000_TOY_MATCH0_INT,
- AU1000_TOY_MATCH1_INT,
- AU1000_TOY_MATCH2_INT,
- AU1000_RTC_INT,
- AU1000_RTC_MATCH0_INT,
- AU1000_RTC_MATCH1_INT,
- AU1000_RTC_MATCH2_INT,
- AU1000_IRDA_TX_INT, /* au1000 */
- AU1000_IRDA_RX_INT, /* au1000 */
- AU1000_USB_DEV_REQ_INT,
- AU1000_USB_DEV_SUS_INT,
- AU1000_USB_HOST_INT,
- AU1000_ACSYNC_INT,
- AU1000_MAC0_DMA_INT,
- AU1000_MAC1_DMA_INT,
- AU1000_I2S_UO_INT, /* au1000 */
- AU1000_AC97C_INT,
- AU1000_GPIO_0,
- AU1000_GPIO_1,
- AU1000_GPIO_2,
- AU1000_GPIO_3,
- AU1000_GPIO_4,
- AU1000_GPIO_5,
- AU1000_GPIO_6,
- AU1000_GPIO_7,
- AU1000_GPIO_8,
- AU1000_GPIO_9,
- AU1000_GPIO_10,
- AU1000_GPIO_11,
- AU1000_GPIO_12,
- AU1000_GPIO_13,
- AU1000_GPIO_14,
- AU1000_GPIO_15,
- AU1000_GPIO_16,
- AU1000_GPIO_17,
- AU1000_GPIO_18,
- AU1000_GPIO_19,
- AU1000_GPIO_20,
- AU1000_GPIO_21,
- AU1000_GPIO_22,
- AU1000_GPIO_23,
- AU1000_GPIO_24,
- AU1000_GPIO_25,
- AU1000_GPIO_26,
- AU1000_GPIO_27,
- AU1000_GPIO_28,
- AU1000_GPIO_29,
- AU1000_GPIO_30,
- AU1000_GPIO_31,
-};
#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART2_ADDR 0xB1300000
#define UART3_ADDR 0xB1400000
#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
#define USB_HOST_CONFIG 0xB017FFFC
+#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
#define AU1000_ETH0_BASE 0xB0500000
#define AU1000_ETH1_BASE 0xB0510000
/* Au1500 */
#ifdef CONFIG_SOC_AU1500
-enum soc_au1500_ints {
- AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
- AU1500_UART0_INT = AU1500_FIRST_INT,
- AU1000_PCI_INTA, /* au1500 */
- AU1000_PCI_INTB, /* au1500 */
- AU1500_UART3_INT,
- AU1000_PCI_INTC, /* au1500 */
- AU1000_PCI_INTD, /* au1500 */
- AU1000_DMA_INT_BASE,
-
- AU1000_TOY_INT = AU1500_FIRST_INT + 14,
- AU1000_TOY_MATCH0_INT,
- AU1000_TOY_MATCH1_INT,
- AU1000_TOY_MATCH2_INT,
- AU1000_RTC_INT,
- AU1000_RTC_MATCH0_INT,
- AU1000_RTC_MATCH1_INT,
- AU1000_RTC_MATCH2_INT,
- AU1500_PCI_ERR_INT,
- AU1500_RESERVED_INT,
- AU1000_USB_DEV_REQ_INT,
- AU1000_USB_DEV_SUS_INT,
- AU1000_USB_HOST_INT,
- AU1000_ACSYNC_INT,
- AU1500_MAC0_DMA_INT,
- AU1500_MAC1_DMA_INT,
- AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
- AU1000_GPIO_0,
- AU1000_GPIO_1,
- AU1000_GPIO_2,
- AU1000_GPIO_3,
- AU1000_GPIO_4,
- AU1000_GPIO_5,
- AU1000_GPIO_6,
- AU1000_GPIO_7,
- AU1000_GPIO_8,
- AU1000_GPIO_9,
- AU1000_GPIO_10,
- AU1000_GPIO_11,
- AU1000_GPIO_12,
- AU1000_GPIO_13,
- AU1000_GPIO_14,
- AU1000_GPIO_15,
- AU1500_GPIO_200,
- AU1500_GPIO_201,
- AU1500_GPIO_202,
- AU1500_GPIO_203,
- AU1500_GPIO_20,
- AU1500_GPIO_204,
- AU1500_GPIO_205,
- AU1500_GPIO_23,
- AU1500_GPIO_24,
- AU1500_GPIO_25,
- AU1500_GPIO_26,
- AU1500_GPIO_27,
- AU1500_GPIO_28,
- AU1500_GPIO_206,
- AU1500_GPIO_207,
- AU1500_GPIO_208_215,
-};
-
-/* shortcuts */
-#define INTA AU1000_PCI_INTA
-#define INTB AU1000_PCI_INTB
-#define INTC AU1000_PCI_INTC
-#define INTD AU1000_PCI_INTD
#define UART0_ADDR 0xB1100000
#define UART3_ADDR 0xB1400000
#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
#define USB_HOST_CONFIG 0xB017fffc
+#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
#define AU1500_ETH0_BASE 0xB1500000
#define AU1500_ETH1_BASE 0xB1510000
/* Au1100 */
#ifdef CONFIG_SOC_AU1100
-enum soc_au1100_ints {
- AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
- AU1100_UART0_INT = AU1100_FIRST_INT,
- AU1100_UART1_INT,
- AU1100_SD_INT,
- AU1100_UART3_INT,
- AU1000_SSI0_INT,
- AU1000_SSI1_INT,
- AU1000_DMA_INT_BASE,
-
- AU1000_TOY_INT = AU1100_FIRST_INT + 14,
- AU1000_TOY_MATCH0_INT,
- AU1000_TOY_MATCH1_INT,
- AU1000_TOY_MATCH2_INT,
- AU1000_RTC_INT,
- AU1000_RTC_MATCH0_INT,
- AU1000_RTC_MATCH1_INT,
- AU1000_RTC_MATCH2_INT,
- AU1000_IRDA_TX_INT,
- AU1000_IRDA_RX_INT,
- AU1000_USB_DEV_REQ_INT,
- AU1000_USB_DEV_SUS_INT,
- AU1000_USB_HOST_INT,
- AU1000_ACSYNC_INT,
- AU1100_MAC0_DMA_INT,
- AU1100_GPIO_208_215,
- AU1100_LCD_INT,
- AU1000_AC97C_INT,
- AU1000_GPIO_0,
- AU1000_GPIO_1,
- AU1000_GPIO_2,
- AU1000_GPIO_3,
- AU1000_GPIO_4,
- AU1000_GPIO_5,
- AU1000_GPIO_6,
- AU1000_GPIO_7,
- AU1000_GPIO_8,
- AU1000_GPIO_9,
- AU1000_GPIO_10,
- AU1000_GPIO_11,
- AU1000_GPIO_12,
- AU1000_GPIO_13,
- AU1000_GPIO_14,
- AU1000_GPIO_15,
- AU1000_GPIO_16,
- AU1000_GPIO_17,
- AU1000_GPIO_18,
- AU1000_GPIO_19,
- AU1000_GPIO_20,
- AU1000_GPIO_21,
- AU1000_GPIO_22,
- AU1000_GPIO_23,
- AU1000_GPIO_24,
- AU1000_GPIO_25,
- AU1000_GPIO_26,
- AU1000_GPIO_27,
- AU1000_GPIO_28,
- AU1000_GPIO_29,
- AU1000_GPIO_30,
- AU1000_GPIO_31,
-};
#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
#define UART3_ADDR 0xB1400000
#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
#define USB_HOST_CONFIG 0xB017FFFC
+#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
#define AU1100_ETH0_BASE 0xB0500000
#define AU1100_MAC0_ENABLE 0xB0520000
#endif /* CONFIG_SOC_AU1100 */
#ifdef CONFIG_SOC_AU1550
-enum soc_au1550_ints {
- AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
- AU1550_UART0_INT = AU1550_FIRST_INT,
- AU1550_PCI_INTA,
- AU1550_PCI_INTB,
- AU1550_DDMA_INT,
- AU1550_CRYPTO_INT,
- AU1550_PCI_INTC,
- AU1550_PCI_INTD,
- AU1550_PCI_RST_INT,
- AU1550_UART1_INT,
- AU1550_UART3_INT,
- AU1550_PSC0_INT,
- AU1550_PSC1_INT,
- AU1550_PSC2_INT,
- AU1550_PSC3_INT,
- AU1000_TOY_INT,
- AU1000_TOY_MATCH0_INT,
- AU1000_TOY_MATCH1_INT,
- AU1000_TOY_MATCH2_INT,
- AU1000_RTC_INT,
- AU1000_RTC_MATCH0_INT,
- AU1000_RTC_MATCH1_INT,
- AU1000_RTC_MATCH2_INT,
-
- AU1550_NAND_INT = AU1550_FIRST_INT + 23,
- AU1550_USB_DEV_REQ_INT,
- AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
- AU1550_USB_DEV_SUS_INT,
- AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
- AU1550_USB_HOST_INT,
- AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
- AU1550_MAC0_DMA_INT,
- AU1550_MAC1_DMA_INT,
- AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
- AU1000_GPIO_1,
- AU1000_GPIO_2,
- AU1000_GPIO_3,
- AU1000_GPIO_4,
- AU1000_GPIO_5,
- AU1000_GPIO_6,
- AU1000_GPIO_7,
- AU1000_GPIO_8,
- AU1000_GPIO_9,
- AU1000_GPIO_10,
- AU1000_GPIO_11,
- AU1000_GPIO_12,
- AU1000_GPIO_13,
- AU1000_GPIO_14,
- AU1000_GPIO_15,
- AU1550_GPIO_200,
- AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
- AU1500_GPIO_16,
- AU1500_GPIO_17,
- AU1500_GPIO_20,
- AU1500_GPIO_21,
- AU1500_GPIO_22,
- AU1500_GPIO_23,
- AU1500_GPIO_24,
- AU1500_GPIO_25,
- AU1500_GPIO_26,
- AU1500_GPIO_27,
- AU1500_GPIO_28,
- AU1500_GPIO_206,
- AU1500_GPIO_207,
- AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
-};
-
-/* shortcuts */
-#define INTA AU1550_PCI_INTA
-#define INTB AU1550_PCI_INTB
-#define INTC AU1550_PCI_INTC
-#define INTD AU1550_PCI_INTD
-
#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART3_ADDR 0xB1400000
#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
#define USB_OHCI_LEN 0x00060000
#define USB_HOST_CONFIG 0xB4027ffc
+#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
#define AU1550_ETH0_BASE 0xB0500000
#define AU1550_ETH1_BASE 0xB0510000
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1550 */
+
#ifdef CONFIG_SOC_AU1200
-enum soc_au1200_ints {
- AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
- AU1200_UART0_INT = AU1200_FIRST_INT,
- AU1200_SWT_INT,
- AU1200_SD_INT,
- AU1200_DDMA_INT,
- AU1200_MAE_BE_INT,
- AU1200_GPIO_200,
- AU1200_GPIO_201,
- AU1200_GPIO_202,
- AU1200_UART1_INT,
- AU1200_MAE_FE_INT,
- AU1200_PSC0_INT,
- AU1200_PSC1_INT,
- AU1200_AES_INT,
- AU1200_CAMERA_INT,
- AU1000_TOY_INT,
- AU1000_TOY_MATCH0_INT,
- AU1000_TOY_MATCH1_INT,
- AU1000_TOY_MATCH2_INT,
- AU1000_RTC_INT,
- AU1000_RTC_MATCH0_INT,
- AU1000_RTC_MATCH1_INT,
- AU1000_RTC_MATCH2_INT,
- AU1200_GPIO_203,
- AU1200_NAND_INT,
- AU1200_GPIO_204,
- AU1200_GPIO_205,
- AU1200_GPIO_206,
- AU1200_GPIO_207,
- AU1200_GPIO_208_215, /* Logical OR of 208:215 */
- AU1200_USB_INT,
- AU1000_USB_HOST_INT = AU1200_USB_INT,
- AU1200_LCD_INT,
- AU1200_MAE_BOTH_INT,
- AU1000_GPIO_0,
- AU1000_GPIO_1,
- AU1000_GPIO_2,
- AU1000_GPIO_3,
- AU1000_GPIO_4,
- AU1000_GPIO_5,
- AU1000_GPIO_6,
- AU1000_GPIO_7,
- AU1000_GPIO_8,
- AU1000_GPIO_9,
- AU1000_GPIO_10,
- AU1000_GPIO_11,
- AU1000_GPIO_12,
- AU1000_GPIO_13,
- AU1000_GPIO_14,
- AU1000_GPIO_15,
- AU1000_GPIO_16,
- AU1000_GPIO_17,
- AU1000_GPIO_18,
- AU1000_GPIO_19,
- AU1000_GPIO_20,
- AU1000_GPIO_21,
- AU1000_GPIO_22,
- AU1000_GPIO_23,
- AU1000_GPIO_24,
- AU1000_GPIO_25,
- AU1000_GPIO_26,
- AU1000_GPIO_27,
- AU1000_GPIO_28,
- AU1000_GPIO_29,
- AU1000_GPIO_30,
- AU1000_GPIO_31,
-};
#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
#define USB_UOC_BASE 0x14020020
#define USB_UOC_LEN 0x20
#define USBMSRMCFG_RDCOMB 30
#define USBMSRMCFG_PFEN 31
-#endif /* CONFIG_SOC_AU1200 */
+#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
-#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
-#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
-#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
-#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
-
-#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
-#define INTX 0xFF /* not valid */
+#endif /* CONFIG_SOC_AU1200 */
/* Programmable Counters 0 and 1 */
#define SYS_BASE 0xB1900000
#define MAC_RX_BUFF3_STATUS 0x30
#define MAC_RX_BUFF3_ADDR 0x34
-/* UARTS 0-3 */
-#define UART_BASE UART0_ADDR
-#ifdef CONFIG_SOC_AU1200
-#define UART_DEBUG_BASE UART1_ADDR
-#else
-#define UART_DEBUG_BASE UART3_ADDR
-#endif
-
#define UART_RX 0 /* Receive buffer */
#define UART_TX 4 /* Transmit buffer */
#define UART_IER 8 /* Interrupt Enable Register */
#define UART_CLK 0x28 /* Baud Rate Clock Divider */
#define UART_MOD_CNTRL 0x100 /* Module Control */
-#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
-#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
-#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
-#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
-#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
-#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
-#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
-
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_SBC 0x40 /* Set break control */
-#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
-#define UART_LCR_EPAR 0x10 /* Even parity select */
-#define UART_LCR_PARITY 0x08 /* Parity Enable */
-#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT 0x40 /* Transmitter empty */
-#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
-#define UART_LSR_BI 0x10 /* Break interrupt indicator */
-#define UART_LSR_FE 0x08 /* Frame error indicator */
-#define UART_LSR_PE 0x04 /* Parity error indicator */
-#define UART_LSR_OE 0x02 /* Overrun error indicator */
-#define UART_LSR_DR 0x01 /* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
-#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
-#define UART_IIR_MSI 0x00 /* Modem status interrupt */
-#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
-#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
-#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
-#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
-#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
-#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
-#define UART_MCR_OUT2 0x08 /* Out2 complement */
-#define UART_MCR_OUT1 0x04 /* Out1 complement */
-#define UART_MCR_RTS 0x02 /* RTS complement */
-#define UART_MCR_DTR 0x01 /* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
-#define UART_MSR_RI 0x40 /* Ring Indicator */
-#define UART_MSR_DSR 0x20 /* Data Set Ready */
-#define UART_MSR_CTS 0x10 /* Clear to Send */
-#define UART_MSR_DDCD 0x08 /* Delta DCD */
-#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
-#define UART_MSR_DDSR 0x02 /* Delta DSR */
-#define UART_MSR_DCTS 0x01 /* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
-
/* SSIO */
#define SSI0_STATUS 0xB1600000
# define SSI_STATUS_BF (1 << 4)
#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
-#define IOMEM_RESOURCE_END 0xffffffff
+#define IOMEM_RESOURCE_END 0xfffffffffULL
#else /* Au1000 and Au1100 and Au1200 */
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
-#define IOMEM_RESOURCE_END 0xffffffff
+#define IOMEM_RESOURCE_END 0xfffffffffULL
#define PCI_IO_START 0
#define PCI_IO_END 0
#endif
-#ifndef _LANGUAGE_ASSEMBLY
-typedef volatile struct {
- /* 0x0000 */ u32 toytrim;
- /* 0x0004 */ u32 toywrite;
- /* 0x0008 */ u32 toymatch0;
- /* 0x000C */ u32 toymatch1;
- /* 0x0010 */ u32 toymatch2;
- /* 0x0014 */ u32 cntrctrl;
- /* 0x0018 */ u32 scratch0;
- /* 0x001C */ u32 scratch1;
- /* 0x0020 */ u32 freqctrl0;
- /* 0x0024 */ u32 freqctrl1;
- /* 0x0028 */ u32 clksrc;
- /* 0x002C */ u32 pinfunc;
- /* 0x0030 */ u32 reserved0;
- /* 0x0034 */ u32 wakemsk;
- /* 0x0038 */ u32 endian;
- /* 0x003C */ u32 powerctrl;
- /* 0x0040 */ u32 toyread;
- /* 0x0044 */ u32 rtctrim;
- /* 0x0048 */ u32 rtcwrite;
- /* 0x004C */ u32 rtcmatch0;
- /* 0x0050 */ u32 rtcmatch1;
- /* 0x0054 */ u32 rtcmatch2;
- /* 0x0058 */ u32 rtcread;
- /* 0x005C */ u32 wakesrc;
- /* 0x0060 */ u32 cpupll;
- /* 0x0064 */ u32 auxpll;
- /* 0x0068 */ u32 reserved1;
- /* 0x006C */ u32 reserved2;
- /* 0x0070 */ u32 reserved3;
- /* 0x0074 */ u32 reserved4;
- /* 0x0078 */ u32 slppwr;
- /* 0x007C */ u32 sleep;
- /* 0x0080 */ u32 reserved5[32];
- /* 0x0100 */ u32 trioutrd;
-#define trioutclr trioutrd
- /* 0x0104 */ u32 reserved6;
- /* 0x0108 */ u32 outputrd;
-#define outputset outputrd
- /* 0x010C */ u32 outputclr;
- /* 0x0110 */ u32 pinstaterd;
-#define pininputen pinstaterd
-} AU1X00_SYS;
-
-static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
-
-#endif
-
#endif
git.openpandora.org / pandora-kernel.git / blobdiff