Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

[pandora-kernel.git] / arch / mips / dec / kn02-irq.c

diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index e0bfcd1..04a367a 100644 (file)
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -4,7 +4,7 @@
  *     DECstation 5000/200 (KN02) Control and Status Register
  *     interrupts.
  *
- *     Copyright (c) 2002, 2003  Maciej W. Rozycki
+ *     Copyright (c) 2002, 2003, 2005  Maciej W. Rozycki
  *
  *     This program is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License
@@ -37,7 +37,8 @@ static int kn02_irq_base;
 
 static inline void unmask_kn02_irq(unsigned int irq)
 {
-       volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
+       volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
+                                                      KN02_CSR);
 
        cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
        *csr = cached_kn02_csr;
@@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq)
 
 static inline void mask_kn02_irq(unsigned int irq)
 {
-       volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
+       volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
+                                                      KN02_CSR);
 
        cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
        *csr = cached_kn02_csr;
@@ -92,7 +94,7 @@ static void end_kn02_irq(unsigned int irq)
                enable_kn02_irq(irq);
 }
 
-static struct hw_interrupt_type kn02_irq_type = {
+static struct irq_chip kn02_irq_type = {
        .typename = "KN02-CSR",
        .startup = startup_kn02_irq,
        .shutdown = shutdown_kn02_irq,
@@ -105,13 +107,14 @@ static struct hw_interrupt_type kn02_irq_type = {
 
 void __init init_kn02_irqs(int base)
 {
-       volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
+       volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
+                                                      KN02_CSR);
        unsigned long flags;
        int i;
 
        /* Mask interrupts. */
        spin_lock_irqsave(&kn02_lock, flags);
-       cached_kn02_csr &= ~KN03_CSR_IOINTEN;
+       cached_kn02_csr &= ~KN02_CSR_IOINTEN;
        *csr = cached_kn02_csr;
        iob();
        spin_unlock_irqrestore(&kn02_lock, flags);
@@ -120,7 +123,7 @@ void __init init_kn02_irqs(int base)
                irq_desc[i].status = IRQ_DISABLED;
                irq_desc[i].action = 0;
                irq_desc[i].depth = 1;
-               irq_desc[i].handler = &kn02_irq_type;
+               irq_desc[i].chip = &kn02_irq_type;
        }
 
        kn02_irq_base = base;