Alchemy: Add UART PM methods.

[pandora-kernel.git] / arch / mips / alchemy / common / power.c

diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 5ef06a1..e5916a5 100644 (file)
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -49,11 +49,6 @@
  * We only have to save/restore registers that aren't otherwise
  * done as part of a driver pm_* function.
  */
-static unsigned int sleep_uart0_inten;
-static unsigned int sleep_uart0_fifoctl;
-static unsigned int sleep_uart0_linectl;
-static unsigned int sleep_uart0_clkdiv;
-static unsigned int sleep_uart0_enable;
 static unsigned int sleep_usb[2];
 static unsigned int sleep_sys_clocks[5];
 static unsigned int sleep_sys_pinfunc;
@@ -62,22 +57,6 @@ static unsigned int sleep_static_memctlr[4][3];
 
 static void save_core_regs(void)
 {
-       extern void save_au1xxx_intctl(void);
-       extern void pm_eth0_shutdown(void);
-
-       /*
-        * Do the serial ports.....these really should be a pm_*
-        * registered function by the driver......but of course the
-        * standard serial driver doesn't understand our Au1xxx
-        * unique registers.
-        */
-       sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
-       sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
-       sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
-       sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
-       sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
-       au_sync();
-
 #ifndef CONFIG_SOC_AU1200
        /* Shutdown USB host/device. */
        sleep_usb[0] = au_readl(USB_HOST_CONFIG);
@@ -175,20 +154,6 @@ static void restore_core_regs(void)
        au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
        au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
        au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
-
-       /*
-        * Enable the UART if it was enabled before sleep.
-        * I guess I should define module control bits........
-        */
-       if (sleep_uart0_enable & 0x02) {
-               au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
-               au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
-               au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
-               au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
-               au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
-               au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
-               au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
-       }
 }
 
 void au_sleep(void)