Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/hch/hfsplus

[pandora-kernel.git] / arch / m68knommu / platform / coldfire / intc-2.c

diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 5598c8b..85daa2b 100644 (file)
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -1,5 +1,11 @@
 /*
- * intc-1.c
+ * intc-2.c
+ *
+ * General interrupt controller code for the many ColdFire cores that use
+ * interrupt controllers with 63 interrupt sources, organized as 56 fully-
+ * programmable + 7 fixed-level interrupt sources. This includes the 523x
+ * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
+ * controllers, and the 547x and 548x families which have only one of them.
  *
  * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
  *
@@ -19,21 +25,37 @@
 #include <asm/traps.h>
 
 /*
- *     Each vector needs a unique priority and level asscoiated with it.
+ * Bit definitions for the ICR family of registers.
+ */
+#define MCFSIM_ICR_LEVEL(l)    ((l)<<3)        /* Level l intr */
+#define MCFSIM_ICR_PRI(p)      (p)             /* Priority p intr */
+
+/*
+ *     Each vector needs a unique priority and level associated with it.
  *     We don't really care so much what they are, we don't rely on the
- *     tranditional priority interrupt scheme of the m68k/ColdFire.
+ *     traditional priority interrupt scheme of the m68k/ColdFire.
  */
-static u8 intc_intpri = 0x36;
+static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
+
+#ifdef MCFICM_INTC1
+#define NR_VECS        128
+#else
+#define NR_VECS        64
+#endif
 
 static void intc_irq_mask(unsigned int irq)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
+       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
                unsigned long imraddr;
                u32 val, imrbit;
 
                irq -= MCFINT_VECBASE;
                imraddr = MCF_IPSBAR;
+#ifdef MCFICM_INTC1
                imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+#else
+               imraddr += MCFICM_INTC0;
+#endif
                imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
                imrbit = 0x1 << (irq & 0x1f);
 
@@ -44,13 +66,17 @@ static void intc_irq_mask(unsigned int irq)
 
 static void intc_irq_unmask(unsigned int irq)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
+       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
                unsigned long intaddr, imraddr, icraddr;
                u32 val, imrbit;
 
                irq -= MCFINT_VECBASE;
                intaddr = MCF_IPSBAR;
+#ifdef MCFICM_INTC1
                intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+#else
+               intaddr += MCFICM_INTC0;
+#endif
                imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
                icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
                imrbit = 0x1 << (irq & 0x1f);
@@ -67,10 +93,16 @@ static void intc_irq_unmask(unsigned int irq)
        }
 }
 
+static int intc_irq_set_type(unsigned int irq, unsigned int type)
+{
+       return 0;
+}
+
 static struct irq_chip intc_irq_chip = {
        .name           = "CF-INTC",
        .mask           = intc_irq_mask,
        .unmask         = intc_irq_unmask,
+       .set_type       = intc_irq_set_type,
 };
 
 void __init init_IRQ(void)
@@ -81,13 +113,14 @@ void __init init_IRQ(void)
 
        /* Mask all interrupt sources */
        __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
+#ifdef MCFICM_INTC1
        __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
+#endif
 
        for (irq = 0; (irq < NR_IRQS); irq++) {
-               irq_desc[irq].status = IRQ_DISABLED;
-               irq_desc[irq].action = NULL;
-               irq_desc[irq].depth = 1;
-               irq_desc[irq].chip = &intc_irq_chip;
+               set_irq_chip(irq, &intc_irq_chip);
+               set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+               set_irq_handler(irq, handle_level_irq);
        }
 }