Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...

[pandora-kernel.git] / arch / blackfin / mach-bf538 / include / mach / irq.h

diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 7a479d2..07ca069 100644 (file)
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -7,38 +7,9 @@
 #ifndef _BF538_IRQ_H_
 #define _BF538_IRQ_H_
 
-/*
- * Interrupt source definitions
-       Event Source    Core Event Name
-       Core        Emulation               **
-       Events         (highest priority)  EMU         0
-       Reset                   RST         1
-       NMI                     NMI         2
-       Exception               EVX         3
-       Reserved                --          4
-       Hardware Error          IVHW        5
-       Core Timer              IVTMR       6 *
-
-       .....
-
-        Software Interrupt 1    IVG14       31
-        Software Interrupt 2    --
-        (lowest priority)  IVG15       32 *
-*/
-
-#define NR_PERI_INTS    (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                        0       /* Emulation */
-#define IRQ_RST                        1       /* reset */
-#define IRQ_NMI                        2       /* Non Maskable */
-#define IRQ_EVX                        3       /* Exception */
-#define IRQ_UNUSED             4       /* - unused interrupt */
-#define IRQ_HWERR              5       /* Hardware Error */
-#define IRQ_CORETMR            6       /* Core timer */
-
-#define BFIN_IRQ(x)            ((x) + 7)
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS           (2 * 32)
 
 #define IRQ_PLL_WAKEUP         BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMA0_ERROR         BFIN_IRQ(1)     /* DMA Error 0 (generic) */
@@ -91,37 +62,26 @@
 
 #define SYS_IRQS               BFIN_IRQ(63)    /* 70 */
 
-#define IRQ_PF0         71
-#define IRQ_PF1         72
-#define IRQ_PF2         73
-#define IRQ_PF3         74
-#define IRQ_PF4         75
-#define IRQ_PF5         76
-#define IRQ_PF6         77
-#define IRQ_PF7         78
-#define IRQ_PF8         79
-#define IRQ_PF9         80
-#define IRQ_PF10        81
-#define IRQ_PF11        82
-#define IRQ_PF12        83
-#define IRQ_PF13        84
-#define IRQ_PF14        85
-#define IRQ_PF15        86
-
-#define GPIO_IRQ_BASE  IRQ_PF0
-
-#define NR_MACH_IRQS   (IRQ_PF15 + 1)
-#define NR_IRQS                (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
+#define IRQ_PF0                        71
+#define IRQ_PF1                        72
+#define IRQ_PF2                        73
+#define IRQ_PF3                        74
+#define IRQ_PF4                        75
+#define IRQ_PF5                        76
+#define IRQ_PF6                        77
+#define IRQ_PF7                        78
+#define IRQ_PF8                        79
+#define IRQ_PF9                        80
+#define IRQ_PF10               81
+#define IRQ_PF11               82
+#define IRQ_PF12               83
+#define IRQ_PF13               84
+#define IRQ_PF14               85
+#define IRQ_PF15               86
+
+#define GPIO_IRQ_BASE          IRQ_PF0
+
+#define NR_MACH_IRQS           (IRQ_PF15 + 1)
 
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS     0
@@ -184,4 +144,5 @@
 #define IRQ_CAN_TX_POS         0
 #define IRQ_MEM1_DMA0_POS      4
 #define IRQ_MEM1_DMA1_POS      8
-#endif                         /* _BF538_IRQ_H_ */
+
+#endif