Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mjg59/platf...
[pandora-kernel.git] / arch / blackfin / mach-bf527 / include / mach / defBF52x_base.h
index 5f97f01..0947503 100644 (file)
 #define FFE                    0x20            /* Force Framing Error On Transmit      */
 
 
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-/* SPI_CTL Masks                                                                                                                                       */
-#define        TIMOD           0x0003          /* Transfer Initiate Mode                                                       */
-#define RDBR_CORE      0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
-#define        TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
-#define RDBR_DMA       0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
-#define TDBR_DMA       0x0003          /*              DMA Write, DMA Until FIFO Full                          */
-#define SZ                     0x0004          /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
-#define GM                     0x0008          /* Get More (When RDBR Full, Overwrite/Discard*)        */
-#define PSSE           0x0010          /* Slave-Select Input Enable                                            */
-#define EMISO          0x0020          /* Enable MISO As Output                                                        */
-#define SIZE           0x0100          /* Size of Words (16/8* Bits)                                           */
-#define LSBF           0x0200          /* LSB First                                                                            */
-#define CPHA           0x0400          /* Clock Phase                                                                          */
-#define CPOL           0x0800          /* Clock Polarity                                                                       */
-#define MSTR           0x1000          /* Master/Slave*                                                                        */
-#define WOM                    0x2000          /* Write Open Drain Master                                                      */
-#define SPE                    0x4000          /* SPI Enable                                                                           */
-
-/* SPI_FLG Masks                                                                                                                                       */
-#define FLS1           0x0002          /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
-#define FLS2           0x0004          /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
-#define FLS3           0x0008          /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
-#define FLS4           0x0010          /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
-#define FLS5           0x0020          /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
-#define FLS6           0x0040          /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
-#define FLS7           0x0080          /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
-#define FLG1           0xFDFF          /* Activates SPI_FLOUT1                                                         */
-#define FLG2           0xFBFF          /* Activates SPI_FLOUT2                                                         */
-#define FLG3           0xF7FF          /* Activates SPI_FLOUT3                                                         */
-#define FLG4           0xEFFF          /* Activates SPI_FLOUT4                                                         */
-#define FLG5           0xDFFF          /* Activates SPI_FLOUT5                                                         */
-#define FLG6           0xBFFF          /* Activates SPI_FLOUT6                                                         */
-#define FLG7           0x7FFF          /* Activates SPI_FLOUT7                                                         */
-
-/* SPI_STAT Masks                                                                                                                                                              */
-#define SPIF           0x0001          /* SPI Finished (Single-Word Transfer Complete)                                 */
-#define MODF           0x0002          /* Mode Fault Error (Another Device Tried To Become Master)             */
-#define TXE                    0x0004          /* Transmission Error (Data Sent With No New Data In TDBR)              */
-#define TXS                    0x0008          /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
-#define RBSY           0x0010          /* Receive Error (Data Received With RDBR Full)                                 */
-#define RXS                    0x0020          /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
-#define TXCOL          0x0040          /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
-
-
 /*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
 /* TIMER_ENABLE Masks                                                                                                  */
 #define TIMEN0                 0x0001          /* Enable Timer 0                                       */
 #define PH14   0x4000
 #define PH15   0x8000
 
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                   */
-#define TSPEN          0x0001          /* Transmit Enable                                                              */
-#define ITCLK          0x0002          /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM     0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW     0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW     0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT         0x0010          /* Transmit Bit Order                                                   */
-#define ITFS           0x0200          /* Internal Transmit Frame Sync Select                  */
-#define TFSR           0x0400          /* Transmit Frame Sync Required Select                  */
-#define DITFS          0x0800          /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS           0x1000          /* Low Transmit Frame Sync Select                               */
-#define LATFS          0x2000          /* Late Transmit Frame Sync Select                              */
-#define TCKFE          0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                 */
-#define SLEN(x)                ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE           0x0100          /* TX Secondary Enable                                                  */
-#define TSFSE          0x0200          /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST          0x0400          /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                   */
-#define RSPEN          0x0001          /* Receive Enable                                                               */
-#define IRCLK          0x0002          /* Internal Receive Clock Select                                */
-#define DTYPE_NORM     0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW     0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW     0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT         0x0010          /* Receive Bit Order                                                    */
-#define IRFS           0x0200          /* Internal Receive Frame Sync Select                   */
-#define RFSR           0x0400          /* Receive Frame Sync Required Select                   */
-#define LRFS           0x1000          /* Low Receive Frame Sync Select                                */
-#define LARFS          0x2000          /* Late Receive Frame Sync Select                               */
-#define RCKFE          0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                   */
-#define SLEN(x)                ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE           0x0100          /* RX Secondary Enable                                                  */
-#define RSFSE          0x0200          /* RX Stereo Frame Sync Enable                                  */
-#define RRFST          0x0400          /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                   */
-#define RXNE           0x0001          /* Receive FIFO Not Empty Status                                */
-#define RUVF           0x0002          /* Sticky Receive Underflow Status                              */
-#define ROVF           0x0004          /* Sticky Receive Overflow Status                               */
-#define TXF                    0x0008          /* Transmit FIFO Full Status                                    */
-#define TUVF           0x0010          /* Sticky Transmit Underflow Status                             */
-#define TOVF           0x0020          /* Sticky Transmit Overflow Status                              */
-#define TXHRE          0x0040          /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                 */
-#define SP_WOFF(x)     ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                           */
-#define SP_WSIZE(x)    (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                  */
-#define REC_BYPASS     0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4     0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16    0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE                0x0004          /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE                0x0008          /* Multichannel DMA Receive Packing                             */
-#define MCMEN          0x0010          /* Multichannel Frame Mode Enable                               */
-#define FSDR           0x0080          /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0          0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1          0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2          0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3          0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4          0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5          0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6          0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7          0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8          0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9          0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10         0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11         0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12         0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13         0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14         0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15         0xF000          /* Multichannel Frame Delay = 15                                */
-
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 /* EBIU_AMGCTL Masks                                                                                                                                   */
 #define AMCKEN                 0x0001          /* Enable CLKOUT                                                                        */