Merge branch 'x86-asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[pandora-kernel.git] / arch / blackfin / Kconfig

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8ea0d94..7faa2f5 100644 (file)
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -274,7 +274,7 @@ config BF_REV_0_0
 
 config BF_REV_0_1
        bool "0.1"
-       depends on (BF52x || (BF54x && !BF54xM))
+       depends on (BF51x || BF52x || (BF54x && !BF54xM))
 
 config BF_REV_0_2
        bool "0.2"
@@ -358,7 +358,7 @@ config MEM_MT48LC8M32B2B5_7
 
 config MEM_MT48LC32M16A2TG_75
        bool
-       depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
+       depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
        default y
 
 config MEM_MT48LC32M8A2_75
@@ -366,6 +366,11 @@ config MEM_MT48LC32M8A2_75
        depends on (BFIN518F_EZBRD)
        default y
 
+config MEM_MT48H32M16LFCJ_75
+       bool
+       depends on (BFIN526_EZBRD)
+       default y
+
 source "arch/blackfin/mach-bf518/Kconfig"
 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
@@ -623,7 +628,6 @@ choice
 config TICKSOURCE_GPTMR0
        bool "Gptimer0 (SCLK domain)"
        select BFIN_GPTIMERS
-       depends on !IPIPE
 
 config TICKSOURCE_CORETMR
        bool "Core timer (CCLK domain)"
@@ -644,6 +648,7 @@ config CYCLES_CLOCKSOURCE
 
 config GPTMR0_CLOCKSOURCE
        bool "Use GPTimer0 as a clocksource (higher rating)"
+       select BFIN_GPTIMERS
        depends on GENERIC_CLOCKEVENTS
        depends on !TICKSOURCE_GPTMR0
 
@@ -908,23 +913,41 @@ endchoice
 
 
 comment "Cache Support"
+
 config BFIN_ICACHE
        bool "Enable ICACHE"
+       default y
+config BFIN_ICACHE_LOCK
+       bool "Enable Instruction Cache Locking"
+       depends on BFIN_ICACHE
+       default n
+config BFIN_EXTMEM_ICACHEABLE
+       bool "Enable ICACHE for external memory"
+       depends on BFIN_ICACHE
+       default y
+config BFIN_L2_ICACHEABLE
+       bool "Enable ICACHE for L2 SRAM"
+       depends on BFIN_ICACHE
+       depends on BF54x || BF561
+       default n
+
 config BFIN_DCACHE
        bool "Enable DCACHE"
+       default y
 config BFIN_DCACHE_BANKA
        bool "Enable only 16k BankA DCACHE - BankB is SRAM"
        depends on BFIN_DCACHE && !BF531
        default n
-config BFIN_ICACHE_LOCK
-       bool "Enable Instruction Cache Locking"
-
-choice
-       prompt "External memory cache policy"
+config BFIN_EXTMEM_DCACHEABLE
+       bool "Enable DCACHE for external memory"
        depends on BFIN_DCACHE
-       default BFIN_WB if !SMP
-       default BFIN_WT if SMP
-config BFIN_WB
+       default y
+choice
+       prompt "External memory DCACHE policy"
+       depends on BFIN_EXTMEM_DCACHEABLE
+       default BFIN_EXTMEM_WRITEBACK if !SMP
+       default BFIN_EXTMEM_WRITETHROUGH if SMP
+config BFIN_EXTMEM_WRITEBACK
        bool "Write back"
        depends on !SMP
        help
@@ -942,7 +965,7 @@ config BFIN_WB
          If you are unsure of the options and you want to be safe,
          then go with Write Through.
 
-config BFIN_WT
+config BFIN_EXTMEM_WRITETHROUGH
        bool "Write through"
        help
          Write Back Policy:
@@ -961,23 +984,26 @@ config BFIN_WT
 
 endchoice
 
+config BFIN_L2_DCACHEABLE
+       bool "Enable DCACHE for L2 SRAM"
+       depends on BFIN_DCACHE
+       depends on BF54x || BF561
+       default n
 choice
-       prompt "L2 SRAM cache policy"
-       depends on (BF54x || BF561)
-       default BFIN_L2_WT
-config BFIN_L2_WB
+       prompt "L2 SRAM DCACHE policy"
+       depends on BFIN_L2_DCACHEABLE
+       default BFIN_L2_WRITEBACK
+config BFIN_L2_WRITEBACK
        bool "Write back"
        depends on !SMP
 
-config BFIN_L2_WT
+config BFIN_L2_WRITETHROUGH
        bool "Write through"
        depends on !SMP
-
-config BFIN_L2_NOT_CACHED
-       bool "Not cached"
-
 endchoice
 
+
+comment "Memory Protection Unit"
 config MPU
        bool "Enable the memory protection unit (EXPERIMENTAL)"
        default n