Merge branch 'driver-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git...

[pandora-kernel.git] / arch / arm / plat-s5p / irq-gpioint.c

diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index f71078e..c65eb79 100644 (file)
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -114,17 +114,18 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
 {
        static int used_gpioint_groups = 0;
        int group = chip->group;
-       struct s5p_gpioint_bank *bank = NULL;
+       struct s5p_gpioint_bank *b, *bank = NULL;
        struct irq_chip_generic *gc;
        struct irq_chip_type *ct;
 
        if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
                return -ENOMEM;
 
-       list_for_each_entry(bank, &banks, list) {
-               if (group >= bank->start &&
-                   group < bank->start + bank->nr_groups)
+       list_for_each_entry(b, &banks, list) {
+               if (group >= b->start && group < b->start + b->nr_groups) {
+                       bank = b;
                        break;
+               }
        }
        if (!bank)
                return -EINVAL;
@@ -162,9 +163,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
        ct->chip.irq_mask = irq_gc_mask_set_bit;
        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
        ct->chip.irq_set_type = s5p_gpioint_set_type,
-       ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
-       ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
-       ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
+       ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
+       ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
+       ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
        irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
                               IRQ_GC_INIT_MASK_CACHE,
                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);