-/*
+ /*
* arch/arm/plat-omap/usb.c -- platform level USB initialization
*
* Copyright (C) 2004 Texas Instruments, Inc.
if (nwires == 0) {
if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+ u32 l;
+
/* pulldown D+/D- */
- USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l &= ~(3 << 1);
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
}
return 0;
}
/* internal transceiver (unavailable on 17xx, 24xx) */
if (!cpu_class_is_omap2() && nwires == 2) {
+ u32 l;
+
// omap_cfg_reg(P9_USB_DP);
// omap_cfg_reg(R8_USB_DM);
* - OTG support on this port not yet written
*/
- USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4);
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l &= ~(7 << 4);
if (!is_device)
- USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+ l |= (3 << 1);
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
return 3 << 16;
}
* with VBUS switching and overcurrent detection.
*/
- if (cpu_class_is_omap1() && nwires != 6)
- USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+ if (cpu_class_is_omap1() && nwires != 6) {
+ u32 l;
+
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l &= ~CONF_USB2_UNI_R;
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
+ }
switch (nwires) {
case 3:
omap_cfg_reg(K20_24XX_USB0_VM);
omap2_usb_devconf_set(0, USB_UNIDIR);
} else {
+ u32 l;
+
omap_cfg_reg(AA9_USB0_VP);
omap_cfg_reg(R9_USB0_VM);
- USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l |= CONF_USB2_UNI_R;
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
}
break;
default:
{
u32 syscon1 = 0;
- if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
- USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
+ if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+ u32 l;
+
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l &= ~CONF_USB1_UNI_R;
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
+ }
if (cpu_is_omap24xx())
omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
syscon1 = 3;
omap_cfg_reg(USB1_VP);
omap_cfg_reg(USB1_VM);
- if (!cpu_is_omap15xx())
- USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
+ if (!cpu_is_omap15xx()) {
+ u32 l;
+
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l |= CONF_USB1_UNI_R;
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
+ }
break;
default:
bad:
if (alt_pingroup || nwires == 0)
return 0;
- if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
- USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+ if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+ u32 l;
+
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l &= ~CONF_USB2_UNI_R;
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
+ }
/* external transceiver */
if (cpu_is_omap15xx()) {
omap_cfg_reg(USB2_VP);
omap_cfg_reg(USB2_VM);
} else {
+ u32 l;
+
omap_cfg_reg(AA9_USB2_VP);
omap_cfg_reg(R9_USB2_VM);
- USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l |= CONF_USB2_UNI_R;
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
}
break;
default:
/*-------------------------------------------------------------------------*/
-#define ULPD_CLOCK_CTRL_REG __REG16(ULPD_CLOCK_CTRL)
-#define ULPD_SOFT_REQ_REG __REG16(ULPD_SOFT_REQ)
-
-
// FIXME correct answer depends on hmc_mode,
// as does (on omap1) any nonzero value for config->otg port number
#ifdef CONFIG_USB_GADGET_OMAP
void __init
omap_otg_init(struct omap_usb_config *config)
{
- u32 syscon = OTG_SYSCON_1_REG & 0xffff;
+ u32 syscon;
int status;
int alt_pingroup = 0;
/* NOTE: no bus or clock setup (yet?) */
- syscon = OTG_SYSCON_1_REG & 0xffff;
+ syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
if (!(syscon & OTG_RESET_DONE))
pr_debug("USB resets not complete?\n");
- // OTG_IRQ_EN_REG = 0;
+ //omap_writew(0, OTG_IRQ_EN);
/* pin muxing and transceiver pinouts */
if (config->pins[0] > 2) /* alt pingroup 2 */
syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
syscon |= omap_usb1_init(config->pins[1]);
syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
- pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
- OTG_SYSCON_1_REG = syscon;
+ pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+ omap_writel(syscon, OTG_SYSCON_1);
syscon = config->hmc_mode;
syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
syscon |= OTG_EN;
#endif
if (cpu_class_is_omap1())
- pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
- pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
- OTG_SYSCON_2_REG = syscon;
+ pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
+ omap_readl(USB_TRANSCEIVER_CTRL));
+ pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
+ omap_writel(syscon, OTG_SYSCON_2);
printk("USB: hmc %d", config->hmc_mode);
if (!alt_pingroup)
printk("\n");
if (cpu_class_is_omap1()) {
+ u16 w;
+
/* leave USB clocks/controllers off until needed */
- ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
- ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
- ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
+ w = omap_readw(ULPD_SOFT_REQ);
+ w &= ~SOFT_USB_CLK_REQ;
+ omap_writew(w, ULPD_SOFT_REQ);
+
+ w = omap_readw(ULPD_CLOCK_CTRL);
+ w &= ~USB_MCLK_EN;
+ w |= DIS_USB_PVCI_CLK;
+ omap_writew(w, ULPD_CLOCK_CTRL);
}
- syscon = OTG_SYSCON_1_REG;
+ syscon = omap_readl(OTG_SYSCON_1);
syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
#ifdef CONFIG_USB_GADGET_OMAP
pr_debug("can't register OTG device, %d\n", status);
}
#endif
- pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
- OTG_SYSCON_1_REG = syscon;
+ pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+ omap_writel(syscon, OTG_SYSCON_1);
status = 0;
}
#ifdef CONFIG_ARCH_OMAP15XX
-#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL)
+/* ULPD_DPLL_CTRL */
#define DPLL_IOB (1 << 13)
#define DPLL_PLL_ENABLE (1 << 4)
#define DPLL_LOCK (1 << 0)
-#define ULPD_APLL_CTRL_REG __REG16(ULPD_APLL_CTRL)
+/* ULPD_APLL_CTRL */
#define APLL_NDPLL_SWITCH (1 << 0)
static void __init omap_1510_usb_init(struct omap_usb_config *config)
{
unsigned int val;
+ u16 w;
omap_usb0_init(config->pins[0], is_usb0_device(config));
omap_usb1_init(config->pins[1]);
printk("\n");
/* use DPLL for 48 MHz function clock */
- pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG,
- ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG);
- ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH;
- ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE;
- ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
- while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK))
+ pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
+ omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
+
+ w = omap_readw(ULPD_APLL_CTRL);
+ w &= ~APLL_NDPLL_SWITCH;
+ omap_writew(w, ULPD_APLL_CTRL);
+
+ w = omap_readw(ULPD_DPLL_CTRL);
+ w |= DPLL_IOB | DPLL_PLL_ENABLE;
+ omap_writew(w, ULPD_DPLL_CTRL);
+
+ w = omap_readw(ULPD_SOFT_REQ);
+ w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
+ omap_writew(w, ULPD_SOFT_REQ);
+
+ while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
cpu_relax();
#ifdef CONFIG_USB_GADGET_OMAP
git.openpandora.org / pandora-kernel.git / blobdiff