#ifndef __OMAP2_GPMC_H
#define __OMAP2_GPMC_H
+/* Maximum Number of Chip Selects */
+#define GPMC_CS_NUM 8
+
#define GPMC_CS_CONFIG1 0x00
#define GPMC_CS_CONFIG2 0x04
#define GPMC_CS_CONFIG3 0x08
#define GPMC_CS_NAND_ADDRESS 0x20
#define GPMC_CS_NAND_DATA 0x24
+/*
+ * The following gpmc registers are being used by
+ * nand driver and hence is defined here.
+ * TBD: Move them to gpmc.c by providing appropriate
+ * methods to read and write into these registers
+ */
+#define GPMC_IRQSTATUS 0x18
+#define GPMC_CONFIG 0x50
+#define GPMC_STATUS 0x54
+#define GPMC_CS0_BASE 0x60
+#define GPMC_CS_SIZE 0x30
+
+
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
u16 access; /* Start-cycle to first data valid delay */
u16 rd_cycle; /* Total read cycle time */
u16 wr_cycle; /* Total write cycle time */
+
+ /* The following are only on OMAP3430 */
+ u16 wr_access; /* WRACCESSTIME */
+ u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
};
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
+extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
extern unsigned long gpmc_get_fclk_period(void);
extern void gpmc_cs_free(int cs);
extern int gpmc_cs_set_reserved(int cs, int reserved);
extern int gpmc_cs_reserved(int cs);
+extern void __init gpmc_init(void);
#endif