Merge branch 'for-linus' of git://neil.brown.name/md

[pandora-kernel.git] / arch / arm / plat-mxc / irq.c

diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 87d253b..1fbe01d 100644 (file)
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -1,51 +1,78 @@
 /*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
  */
 
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <asm/hardware.h>
+#include <linux/irq.h>
 #include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
 #include <asm/arch/common.h>
 
-/*!
- * Disable interrupt number "irq" in the AVIC
- *
- * @param  irq          interrupt source number
- */
+#define AVIC_BASE              IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL           (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK            (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM          (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM         (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH                (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL                (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH          (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL          (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY7       (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6       (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5       (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4       (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3       (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2       (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1       (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0       (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIVECSR           (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR           (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH           (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL           (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH           (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL           (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH            (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL            (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH            (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL            (AVIC_BASE + 0x64)      /* fast int pending low */
+
+#define SYSTEM_PREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH                3
+#define IIM_PROD_REV_LEN       5
+
+/* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
        __raw_writel(irq, AVIC_INTDISNUM);
 }
 
-/*!
- * Enable interrupt number "irq" in the AVIC
- *
- * @param  irq          interrupt source number
- */
+/* Enable interrupt number "irq" in the AVIC */
 static void mxc_unmask_irq(unsigned int irq)
 {
        __raw_writel(irq, AVIC_INTENNUM);
 }
 
 static struct irq_chip mxc_avic_chip = {
-       .mask_ack = mxc_mask_irq,
+       .ack = mxc_mask_irq,
        .mask = mxc_mask_irq,
        .unmask = mxc_unmask_irq,
 };
 
-/*!
+/*
  * This function initializes the AVIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
  * to the kernel for each interrupt source.
@@ -79,5 +106,8 @@ void __init mxc_init_irq(void)
        reg |= (0xF << 28);
        __raw_writel(reg, AVIC_NIPRIORITY6);
 
+       /* init architectures chained interrupt handler */
+       mxc_register_gpios();
+
        printk(KERN_INFO "MXC IRQ initialized\n");
 }