Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

[pandora-kernel.git] / arch / arm / plat-mxc / include / mach / mx51.h

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index c99eeab..2af7a10 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -64,13 +64,13 @@
 #define MX51_SPBA0_BASE_ADDR_VIRT      0xfb100000
 #define MX51_SPBA0_SIZE                        SZ_1M
 
-#define MX51_MMC_SDHC1_BASE_ADDR       (MX51_SPBA0_BASE_ADDR + 0x04000)
-#define MX51_MMC_SDHC2_BASE_ADDR       (MX51_SPBA0_BASE_ADDR + 0x08000)
+#define MX51_ESDHC1_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x04000)
+#define MX51_ESDHC2_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x08000)
 #define MX51_UART3_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x0c000)
 #define MX51_ECSPI1_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x10000)
 #define MX51_SSI2_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x14000)
-#define MX51_MMC_SDHC3_BASE_ADDR       (MX51_SPBA0_BASE_ADDR + 0x20000)
-#define MX51_MMC_SDHC4_BASE_ADDR       (MX51_SPBA0_BASE_ADDR + 0x24000)
+#define MX51_ESDHC3_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x20000)
+#define MX51_ESDHC4_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x24000)
 #define MX51_SPDIF_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x28000)
 #define MX51_ATA_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x30000)
 #define MX51_SLIM_DMA_BASE_ADDR                (MX51_SPBA0_BASE_ADDR + 0x34000)
@@ -140,7 +140,7 @@
 #define MX51_ATA_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xe0000)
 #define MX51_SIM_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xe4000)
 #define MX51_SSI3BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xe8000)
-#define MX51_MXC_FEC_BASE_ADDR         (MX51_AIPS2_BASE_ADDR + 0xec000)
+#define MX51_FEC_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xec000)
 #define MX51_TVE_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xf0000)
 #define MX51_VPU_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xf4000)
 #define MX51_SAHARA_BASE_ADDR          (MX51_AIPS2_BASE_ADDR + 0xf8000)
@@ -280,12 +280,12 @@
  */
 #define MX51_MXC_INT_BASE              0
 #define MX51_MXC_INT_RESV0             0
-#define MX51_MXC_INT_MMC_SDHC1         1
-#define MX51_MXC_INT_MMC_SDHC2         2
-#define MX51_MXC_INT_MMC_SDHC3         3
-#define MX51_MXC_INT_MMC_SDHC4         4
+#define MX51_INT_ESDHC1                        1
+#define MX51_INT_ESDHC2                        2
+#define MX51_INT_ESDHC3                        3
+#define MX51_INT_ESDHC4                        4
 #define MX51_MXC_INT_RESV5             5
-#define MX51_MXC_INT_SDMA              6
+#define MX51_INT_SDMA                  6
 #define MX51_MXC_INT_IOMUX             7
 #define MX51_INT_NFC                   8
 #define MX51_MXC_INT_VPU               9
@@ -366,7 +366,7 @@
 #define MX51_MXC_INT_GPU2_IRQ          84
 #define MX51_MXC_INT_GPU2_BUSY         85
 #define MX51_MXC_INT_RESV86            86
-#define MX51_MXC_INT_FEC               87
+#define MX51_INT_FEC                   87
 #define MX51_MXC_INT_OWIRE             88
 #define MX51_MXC_INT_CTI1_TG2          89
 #define MX51_MXC_INT_SJC               90