Merge branch 'x86/amd-nb' into x86/apic-cleanups

[pandora-kernel.git] / arch / arm / plat-mxc / include / mach / mx35.h

diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index af3038c..6267cff 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,5 +1,6 @@
 #ifndef __MACH_MX35_H__
 #define __MACH_MX35_H__
+
 /*
  * IRAM
  */
@@ -52,6 +53,9 @@
 #define MX35_GPIO3_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xa4000)
 #define MX35_SCC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xac000)
 #define MX35_RNGA_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_ESDHC1_BASE_ADDR                  (MX35_AIPS2_BASE_ADDR + 0xb4000)
+#define MX35_ESDHC2_BASE_ADDR                  (MX35_AIPS2_BASE_ADDR + 0xb8000)
+#define MX35_ESDHC3_BASE_ADDR                  (MX35_AIPS2_BASE_ADDR + 0xbc000)
 #define MX35_IPU_CTRL_BASE_ADDR                        (MX35_AIPS2_BASE_ADDR + 0xc0000)
 #define MX35_AUDMUX_BASE_ADDR                  (MX35_AIPS2_BASE_ADDR + 0xc4000)
 #define MX35_GPIO1_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xcc000)
@@ -63,6 +67,8 @@
 #define MX35_CAN1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xe4000)
 #define MX35_CAN2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xe8000)
 #define MX35_RTIC_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_IIM_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xf0000)
+
 #define MX35_OTG_BASE_ADDR             0x53ff4000
 
 #define MX35_ROMP_BASE_ADDR            0x60000000
@@ -122,9 +128,9 @@
 #define MX35_INT_I2C3          3
 #define MX35_INT_I2C2          4
 #define MX35_INT_RTIC          6
-#define MX35_INT_MMC_SDHC1     7
-#define MX35_INT_MMC_SDHC2     8
-#define MX35_INT_MMC_SDHC3     9
+#define MX35_INT_ESDHC1                7
+#define MX35_INT_ESDHC2                8
+#define MX35_INT_ESDHC3                9
 #define MX35_INT_I2C1          10
 #define MX35_INT_SSI1          11
 #define MX35_INT_SSI2          12
@@ -145,7 +151,7 @@
 #define MX35_INT_GPT           29
 #define MX35_INT_POWER_FAIL    30
 #define MX35_INT_UART2         32
-#define MX35_INT_NANDFC                33
+#define MX35_INT_NFC           33
 #define MX35_INT_SDMA          34
 #define MX35_INT_USBHS         35
 #define MX35_INT_USBOTG                37
@@ -173,30 +179,24 @@
 #define MX35_INT_EXT_WDOG      62
 #define MX35_INT_EXT_TV                63
 
+#define MX35_DMA_REQ_SSI2_RX1   22
+#define MX35_DMA_REQ_SSI2_TX1   23
+#define MX35_DMA_REQ_SSI2_RX0   24
+#define MX35_DMA_REQ_SSI2_TX0   25
+#define MX35_DMA_REQ_SSI1_RX1   26
+#define MX35_DMA_REQ_SSI1_TX1   27
+#define MX35_DMA_REQ_SSI1_RX0   28
+#define MX35_DMA_REQ_SSI1_TX0   29
+
 #define MX35_PROD_SIGNATURE            0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
-#define MX35_CHIP_REV_1_0              0x10
-#define MX35_CHIP_REV_1_1              0x11
-#define MX35_CHIP_REV_1_2              0x12
-#define MX35_CHIP_REV_1_3              0x13
-#define MX35_CHIP_REV_2_0              0x20
-#define MX35_CHIP_REV_2_1              0x21
-#define MX35_CHIP_REV_2_2              0x22
-#define MX35_CHIP_REV_2_3              0x23
-#define MX35_CHIP_REV_3_0              0x30
-#define MX35_CHIP_REV_3_1              0x31
-#define MX35_CHIP_REV_3_2              0x32
-
-#define MX35_SYSTEM_REV_MIN            MX35_CHIP_REV_1_0
+#define MX35_SYSTEM_REV_MIN            MX3x_CHIP_REV_1_0
 #define MX35_SYSTEM_REV_NUM            3
 
 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
 /* these should go away */
 #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
 #define MXC_INT_OWIRE MX35_INT_OWIRE
-#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
-#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
 #define MXC_INT_GPU2D MX35_INT_GPU2D
 #define MXC_INT_ASRC MX35_INT_ASRC
 #define MXC_INT_USBHS MX35_INT_USBHS