#define __ASM_ARCH_MXC_IRQS_H__
/*
- * So far all i.MX SoCs have 64 internal interrupts
+ * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
*/
+#ifdef CONFIG_MXC_TZIC
+#define MXC_INTERNAL_IRQS 128
+#else
#define MXC_INTERNAL_IRQS 64
+#endif
#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
-#if defined CONFIG_ARCH_MX1
-#define MXC_GPIO_IRQS (32 * 4)
-#elif defined CONFIG_ARCH_MX2
+/* these are ordered by size to support multi-SoC kernels */
+#if defined CONFIG_ARCH_MX2
#define MXC_GPIO_IRQS (32 * 6)
-#elif defined CONFIG_ARCH_MX3
-#define MXC_GPIO_IRQS (32 * 3)
+#elif defined CONFIG_ARCH_MX1
+#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MX25
#define MXC_GPIO_IRQS (32 * 4)
+#elif defined CONFIG_ARCH_MX5
+#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MXC91231
#define MXC_GPIO_IRQS (32 * 4)
+#elif defined CONFIG_ARCH_MX3
+#define MXC_GPIO_IRQS (32 * 3)
#endif
/*
#else
#define MX3_IPU_IRQS 0
#endif
+/* REVISIT: Add IPU irqs on IMX51 */
#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)