Merge branch 'agp-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...

[pandora-kernel.git] / arch / arm / plat-mxc / gpio.c

diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 89e9579..cfc4a8b 100644 (file)
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -29,6 +29,23 @@
 static struct mxc_gpio_port *mxc_gpio_ports;
 static int gpio_table_size;
 
+#define cpu_is_mx1_mx2()       (cpu_is_mx1() || cpu_is_mx2())
+
+#define GPIO_DR                (cpu_is_mx1_mx2() ? 0x1c : 0x00)
+#define GPIO_GDIR      (cpu_is_mx1_mx2() ? 0x00 : 0x04)
+#define GPIO_PSR       (cpu_is_mx1_mx2() ? 0x24 : 0x08)
+#define GPIO_ICR1      (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
+#define GPIO_ICR2      (cpu_is_mx1_mx2() ? 0x2C : 0x10)
+#define GPIO_IMR       (cpu_is_mx1_mx2() ? 0x30 : 0x14)
+#define GPIO_ISR       (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+#define GPIO_ISR       (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+
+#define GPIO_INT_LOW_LEV       (cpu_is_mx1_mx2() ? 0x3 : 0x0)
+#define GPIO_INT_HIGH_LEV      (cpu_is_mx1_mx2() ? 0x2 : 0x1)
+#define GPIO_INT_RISE_EDGE     (cpu_is_mx1_mx2() ? 0x0 : 0x2)
+#define GPIO_INT_FALL_EDGE     (cpu_is_mx1_mx2() ? 0x1 : 0x3)
+#define GPIO_INT_NONE          0x4
+
 /* Note: This driver assumes 32 GPIOs are handled in one register */
 
 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
@@ -64,6 +81,8 @@ static void gpio_unmask_irq(u32 irq)
        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
 }
 
+static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
+
 static int gpio_set_irq_type(u32 irq, u32 type)
 {
        u32 gpio = irq_to_gpio(irq);
@@ -72,6 +91,7 @@ static int gpio_set_irq_type(u32 irq, u32 type)
        int edge;
        void __iomem *reg = port->base;
 
+       port->both_edges &= ~(1 << (gpio & 31));
        switch (type) {
        case IRQ_TYPE_EDGE_RISING:
                edge = GPIO_INT_RISE_EDGE;
@@ -79,13 +99,24 @@ static int gpio_set_irq_type(u32 irq, u32 type)
        case IRQ_TYPE_EDGE_FALLING:
                edge = GPIO_INT_FALL_EDGE;
                break;
+       case IRQ_TYPE_EDGE_BOTH:
+               val = mxc_gpio_get(&port->chip, gpio & 31);
+               if (val) {
+                       edge = GPIO_INT_LOW_LEV;
+                       pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
+               } else {
+                       edge = GPIO_INT_HIGH_LEV;
+                       pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
+               }
+               port->both_edges |= 1 << (gpio & 31);
+               break;
        case IRQ_TYPE_LEVEL_LOW:
                edge = GPIO_INT_LOW_LEV;
                break;
        case IRQ_TYPE_LEVEL_HIGH:
                edge = GPIO_INT_HIGH_LEV;
                break;
-       default:        /* this includes IRQ_TYPE_EDGE_BOTH */
+       default:
                return -EINVAL;
        }
 
@@ -98,6 +129,34 @@ static int gpio_set_irq_type(u32 irq, u32 type)
        return 0;
 }
 
+static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
+{
+       void __iomem *reg = port->base;
+       u32 bit, val;
+       int edge;
+
+       reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+       bit = gpio & 0xf;
+       val = __raw_readl(reg);
+       edge = (val >> (bit << 1)) & 3;
+       val &= ~(0x3 << (bit << 1));
+       switch (edge) {
+       case GPIO_INT_HIGH_LEV:
+               edge = GPIO_INT_LOW_LEV;
+               pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
+               break;
+       case GPIO_INT_LOW_LEV:
+               edge = GPIO_INT_HIGH_LEV;
+               pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
+               break;
+       default:
+               pr_err("mxc: invalid configuration for GPIO %d: %x\n",
+                      gpio, edge);
+               return;
+       }
+       __raw_writel(val | (edge << (bit << 1)), reg);
+}
+
 /* handle n interrupts in one status register */
 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 {
@@ -105,17 +164,21 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 
        gpio_irq_no = port->virtual_irq_start;
        for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
+               u32 gpio = irq_to_gpio(gpio_irq_no);
 
                if ((irq_stat & 1) == 0)
                        continue;
 
                BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
+
+               if (port->both_edges & (1 << (gpio & 31)))
+                       mxc_flip_edge(port, gpio);
+
                irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
                                &irq_desc[gpio_irq_no]);
        }
 }
 
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
 /* MX1 and MX3 has one interrupt *per* gpio port */
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -127,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 
        mxc_gpio_irq_handler(port, irq_stat);
 }
-#endif
 
-#ifdef CONFIG_ARCH_MX2
 /* MX2 has one interrupt *for all* gpio ports */
 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -148,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
                        mxc_gpio_irq_handler(&port[i], irq_stat);
        }
 }
-#endif
 
 static struct irq_chip gpio_irq_chip = {
        .ack = gpio_ack_irq,
@@ -237,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                /* its a serious configuration bug when it fails */
                BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
-               /* setup one handler for each entry */
-               set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
-               set_irq_data(port[i].irq, &port[i]);
-#endif
+               if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
+                       /* setup one handler for each entry */
+                       set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
+                       set_irq_data(port[i].irq, &port[i]);
+               }
+       }
+
+       if (cpu_is_mx2()) {
+               /* setup one handler for all GPIO interrupts */
+               set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+               set_irq_data(port[0].irq, port);
        }
 
-#ifdef CONFIG_ARCH_MX2
-       /* setup one handler for all GPIO interrupts */
-       set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-       set_irq_data(port[0].irq, port);
-#endif
        return 0;
 }