Merge branch 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6

[pandora-kernel.git] / arch / arm / plat-mxc / gpio.c

diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 57d5985..7a10724 100644 (file)
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
        u32 irq_stat;
-       struct mxc_gpio_port *port = get_irq_data(irq);
+       struct mxc_gpio_port *port = irq_get_handler_data(irq);
 
        irq_stat = __raw_readl(port->base + GPIO_ISR) &
                        __raw_readl(port->base + GPIO_IMR);
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
        int i;
        u32 irq_msk, irq_stat;
-       struct mxc_gpio_port *port = get_irq_data(irq);
+       struct mxc_gpio_port *port = irq_get_handler_data(irq);
 
        /* walk through all interrupt status registers */
        for (i = 0; i < gpio_table_size; i++) {
@@ -311,8 +311,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                __raw_writel(~0, port[i].base + GPIO_ISR);
                for (j = port[i].virtual_irq_start;
                        j < port[i].virtual_irq_start + 32; j++) {
-                       set_irq_chip(j, &gpio_irq_chip);
-                       set_irq_handler(j, handle_level_irq);
+                       irq_set_chip_and_handler(j, &gpio_irq_chip,
+                                                handle_level_irq);
                        set_irq_flags(j, IRQF_VALID);
                }
 
@@ -331,21 +331,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 
                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
                        /* setup one handler for each entry */
-                       set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
-                       set_irq_data(port[i].irq, &port[i]);
+                       irq_set_chained_handler(port[i].irq,
+                                               mx3_gpio_irq_handler);
+                       irq_set_handler_data(port[i].irq, &port[i]);
                        if (port[i].irq_high) {
                                /* setup handler for GPIO 16 to 31 */
-                               set_irq_chained_handler(port[i].irq_high,
-                                               mx3_gpio_irq_handler);
-                               set_irq_data(port[i].irq_high, &port[i]);
+                               irq_set_chained_handler(port[i].irq_high,
+                                                       mx3_gpio_irq_handler);
+                               irq_set_handler_data(port[i].irq_high,
+                                                    &port[i]);
                        }
                }
        }
 
        if (cpu_is_mx2()) {
                /* setup one handler for all GPIO interrupts */
-               set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-               set_irq_data(port[0].irq, port);
+               irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+               irq_set_handler_data(port[0].irq, port);
        }
 
        return 0;