Merge branch 'next/timer' of git://git.linaro.org/people/arnd/arm-soc

[pandora-kernel.git] / arch / arm / mm / proc-xscale.S

diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index fbc06e5..3277904 100644 (file)
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -520,24 +520,23 @@ ENTRY(cpu_xscale_set_pte_ext)
        .align
 
 .globl cpu_xscale_suspend_size
-.equ   cpu_xscale_suspend_size, 4 * 7
+.equ   cpu_xscale_suspend_size, 4 * 6
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_xscale_do_suspend)
-       stmfd   sp!, {r4 - r10, lr}
+       stmfd   sp!, {r4 - r9, lr}
        mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
        mrc     p15, 0, r5, c15, c1, 0  @ CP access reg
        mrc     p15, 0, r6, c13, c0, 0  @ PID
        mrc     p15, 0, r7, c3, c0, 0   @ domain ID
-       mrc     p15, 0, r8, c2, c0, 0   @ translation table base addr
-       mrc     p15, 0, r9, c1, c1, 0   @ auxiliary control reg
-       mrc     p15, 0, r10, c1, c0, 0  @ control reg
+       mrc     p15, 0, r8, c1, c1, 0   @ auxiliary control reg
+       mrc     p15, 0, r9, c1, c0, 0   @ control reg
        bic     r4, r4, #2              @ clear frequency change bit
-       stmia   r0, {r4 - r10}          @ store cp regs
-       ldmfd   sp!, {r4 - r10, pc}
+       stmia   r0, {r4 - r9}           @ store cp regs
+       ldmfd   sp!, {r4 - r9, pc}
 ENDPROC(cpu_xscale_do_suspend)
 
 ENTRY(cpu_xscale_do_resume)
-       ldmia   r0, {r4 - r10}          @ load cp regs
+       ldmia   r0, {r4 - r9}           @ load cp regs
        mov     ip, #0
        mcr     p15, 0, ip, c8, c7, 0   @ invalidate I & D TLBs
        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I & D caches, BTB
@@ -545,13 +544,9 @@ ENTRY(cpu_xscale_do_resume)
        mcr     p15, 0, r5, c15, c1, 0  @ CP access reg
        mcr     p15, 0, r6, c13, c0, 0  @ PID
        mcr     p15, 0, r7, c3, c0, 0   @ domain ID
-       mcr     p15, 0, r8, c2, c0, 0   @ translation table base addr
-       mcr     p15, 0, r9, c1, c1, 0   @ auxiliary control reg
-       mov     r0, r10                 @ control register
-       mov     r2, r8, lsr #14         @ get TTB0 base
-       mov     r2, r2, lsl #14
-       ldr     r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
-                    PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
+       mcr     p15, 0, r1, c2, c0, 0   @ translation table base addr
+       mcr     p15, 0, r8, c1, c1, 0   @ auxiliary control reg
+       mov     r0, r9                  @ control register
        b       cpu_resume_mmu
 ENDPROC(cpu_xscale_do_resume)
 #endif