Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/teigland/dlm

[pandora-kernel.git] / arch / arm / mm / proc-v7.S

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a08d9d2..f3fa1c3 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,17 +19,23 @@
 
 #include "proc-macros.S"
 
-#define TTB_C          (1 << 0)
 #define TTB_S          (1 << 1)
 #define TTB_RGN_NC     (0 << 3)
 #define TTB_RGN_OC_WBWA        (1 << 3)
 #define TTB_RGN_OC_WT  (2 << 3)
 #define TTB_RGN_OC_WB  (3 << 3)
+#define TTB_NOS                (1 << 5)
+#define TTB_IRGN_NC    ((0 << 0) | (0 << 6))
+#define TTB_IRGN_WBWA  ((0 << 0) | (1 << 6))
+#define TTB_IRGN_WT    ((1 << 0) | (0 << 6))
+#define TTB_IRGN_WB    ((1 << 0) | (1 << 6))
 
 #ifndef CONFIG_SMP
-#define TTB_FLAGS      TTB_C|TTB_RGN_OC_WB             @ mark PTWs cacheable, outer WB
+/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
+#define TTB_FLAGS      TTB_IRGN_WB|TTB_RGN_OC_WB
 #else
-#define TTB_FLAGS      TTB_C|TTB_S|TTB_RGN_OC_WBWA     @ mark PTWs cacheable and shared, outer WBWA
+/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
+#define TTB_FLAGS      TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
 #endif
 
 ENTRY(cpu_v7_proc_init)
@@ -121,7 +127,9 @@ ENDPROC(cpu_v7_switch_mm)
  */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
+ ARM(  str     r1, [r0], #-2048        )       @ linux version
+ THUMB(        str     r1, [r0]                )       @ linux version
+ THUMB(        sub     r0, r0, #2048           )
 
        bic     r3, r1, #0x000003f0
        bic     r3, r3, #PTE_TYPE_MASK
@@ -176,8 +184,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-       mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
-       orr     r0, r0, #(0x1 << 6)
+       mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode and
+       orr     r0, r0, #(1 << 6) | (1 << 0)    @ TLB ops broadcasting
        mcr     p15, 0, r0, c1, c0, 1
 #endif
        adr     r12, __v7_setup_stack           @ the local stack
@@ -226,28 +234,60 @@ __v7_setup:
        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
        mov     r10, #0x1f                      @ domains 0, 1 = manager
        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
-#endif
-       ldr     r5, =0xff0aa1a8
-       ldr     r6, =0x40e040e0
+       /*
+        * Memory region attributes with SCTLR.TRE=1
+        *
+        *   n = TEX[0],C,B
+        *   TR = PRRR[2n+1:2n]         - memory type
+        *   IR = NMRR[2n+1:2n]         - inner cacheable property
+        *   OR = NMRR[2n+17:2n+16]     - outer cacheable property
+        *
+        *                      n       TR      IR      OR
+        *   UNCACHED           000     00
+        *   BUFFERABLE         001     10      00      00
+        *   WRITETHROUGH       010     10      10      10
+        *   WRITEBACK          011     10      11      11
+        *   reserved           110
+        *   WRITEALLOC         111     10      01      01
+        *   DEV_SHARED         100     01
+        *   DEV_NONSHARED      100     01
+        *   DEV_WC             001     10
+        *   DEV_CACHED         011     10
+        *
+        * Other attributes:
+        *
+        *   DS0 = PRRR[16] = 0         - device shareable property
+        *   DS1 = PRRR[17] = 1         - device shareable property
+        *   NS0 = PRRR[18] = 0         - normal shareable property
+        *   NS1 = PRRR[19] = 1         - normal shareable property
+        *   NOS = PRRR[24+n] = 1       - not outer shareable
+        */
+       ldr     r5, =0xff0a81a8                 @ PRRR
+       ldr     r6, =0x40e040e0                 @ NMRR
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
+#endif
        adr     r5, v7_crval
        ldmia   r5, {r5, r6}
+#ifdef CONFIG_CPU_ENDIAN_BE8
+       orr     r6, r6, #1 << 25                @ big-endian page tables
+#endif
        mrc     p15, 0, r0, c1, c0, 0           @ read control register
        bic     r0, r0, r5                      @ clear bits them
        orr     r0, r0, r6                      @ set them
+ THUMB(        orr     r0, r0, #1 << 30        )       @ Thumb exceptions
        mov     pc, lr                          @ return to head.S:__ret
 ENDPROC(__v7_setup)
 
        /*   AT
-        *  TFR   EV X F   I D LR
-        * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
+        *  TFR   EV X F   I D LR    S
+        * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
         * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
-        *    1    0 110       0011 1.00 .111 1101 < we want
+        *    1    0 110       0011 1100 .111 1101 < we want
         */
        .type   v7_crval, #object
 v7_crval:
-       crval   clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
+       crval   clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
 
 __v7_setup_stack:
        .space  4 * 11                          @ 11 registers