ARM: LPAE: MMU setup for the 3-level page table format

[pandora-kernel.git] / arch / arm / mm / proc-v7.S

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index e2d6ffa..69bcd4a 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,7 +19,11 @@
 
 #include "proc-macros.S"
 
+#ifdef CONFIG_ARM_LPAE
+#include "proc-v7-3level.S"
+#else
 #include "proc-v7-2level.S"
+#endif
 
 ENTRY(cpu_v7_proc_init)
        mov     pc, lr
@@ -87,7 +91,7 @@ ENDPROC(cpu_v7_dcache_clean_area)
 
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl cpu_v7_suspend_size
-.equ   cpu_v7_suspend_size, 4 * 7
+.equ   cpu_v7_suspend_size, 4 * 8
 #ifdef CONFIG_ARM_CPU_SUSPEND
 ENTRY(cpu_v7_do_suspend)
        stmfd   sp!, {r4 - r10, lr}
@@ -96,10 +100,11 @@ ENTRY(cpu_v7_do_suspend)
        stmia   r0!, {r4 - r5}
        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
        mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
+       mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
        mrc     p15, 0, r8, c1, c0, 0   @ Control register
        mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
        mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
-       stmia   r0, {r6 - r10}
+       stmia   r0, {r6 - r11}
        ldmfd   sp!, {r4 - r10, pc}
 ENDPROC(cpu_v7_do_suspend)
 
@@ -111,13 +116,15 @@ ENTRY(cpu_v7_do_resume)
        ldmia   r0!, {r4 - r5}
        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
        mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
-       ldmia   r0, {r6 - r10}
+       ldmia   r0, {r6 - r11}
        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
+#ifndef CONFIG_ARM_LPAE
        ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
        ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
+#endif
        mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
        mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
-       mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+       mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
        teq     r4, r9                  @ Is it already set?
        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
@@ -303,11 +310,11 @@ __v7_setup_stack:
         */
 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
        ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
-                       PMD_FLAGS_SMP | \mm_mmuflags)
+                       PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
        ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
-                       PMD_FLAGS_UP | \mm_mmuflags)
-       .long   PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
-               PMD_SECT_AP_READ | \io_mmuflags
+                       PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
+       .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
        W(b)    \initfunc
        .long   cpu_arch_name
        .long   cpu_elf_name
@@ -320,6 +327,7 @@ __v7_setup_stack:
        .long   v7_cache_fns
 .endm
 
+#ifndef CONFIG_ARM_LPAE
        /*
         * ARM Ltd. Cortex A5 processor.
         */
@@ -339,6 +347,7 @@ __v7_ca9mp_proc_info:
        .long   0xff0ffff0
        __v7_proc __v7_ca9mp_setup
        .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+#endif /* CONFIG_ARM_LPAE */
 
        /*
         * ARM Ltd. Cortex A15 processor.