Merge branch 'stable-3.2' into pandora-3.2-stable

[pandora-kernel.git] / arch / arm / mm / proc-v7.S

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a0145a1..2dcafbe 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -271,10 +271,6 @@ ENDPROC(cpu_v7_do_resume)
  *     Initialise TLB, Caches, and MMU state ready to switch the MMU
  *     on.  Return in r0 the new CP15 C1 control register setting.
  *
- *     We automatically detect if we have a Harvard cache, and use the
- *     Harvard cache control instructions insead of the unified cache
- *     control instructions.
- *
  *     This should be able to cover all ARMv7 cores.
  *
  *     It is assumed that:
@@ -356,9 +352,7 @@ __v7_setup:
        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
 #ifdef CONFIG_ARM_ERRATA_743622
-       teq     r6, #0x20                       @ present in r2p0
-       teqne   r6, #0x21                       @ present in r2p1
-       teqne   r6, #0x22                       @ present in r2p2
+       teq     r5, #0x00200000                 @ only present in r2p*
        mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
        orreq   r10, r10, #1 << 6               @ set bit #6
        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
@@ -373,9 +367,7 @@ __v7_setup:
 #endif
 
 3:     mov     r10, #0
-#ifdef HARVARD_CACHE
        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
-#endif
        dsb
 #ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs