Merge branch 'master' of ../mmc

[pandora-kernel.git] / arch / arm / mm / proc-v7.S

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 34e4240..d1ebec4 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -20,9 +20,17 @@
 
 #define TTB_C          (1 << 0)
 #define TTB_S          (1 << 1)
+#define TTB_RGN_NC     (0 << 3)
+#define TTB_RGN_OC_WBWA        (1 << 3)
 #define TTB_RGN_OC_WT  (2 << 3)
 #define TTB_RGN_OC_WB  (3 << 3)
 
+#ifndef CONFIG_SMP
+#define TTB_FLAGS      TTB_C|TTB_RGN_OC_WB             @ mark PTWs cacheable, outer WB
+#else
+#define TTB_FLAGS      TTB_C|TTB_S|TTB_RGN_OC_WBWA     @ mark PTWs cacheable and shared, outer WBWA
+#endif
+
 ENTRY(cpu_v7_proc_init)
        mov     pc, lr
 ENDPROC(cpu_v7_proc_init)
@@ -55,6 +63,7 @@ ENDPROC(cpu_v7_reset)
  *     IRQs are already disabled.
  */
 ENTRY(cpu_v7_do_idle)
+       dsb                                     @ WFI may enter a low-power mode
        wfi
        mov     pc, lr
 ENDPROC(cpu_v7_do_idle)
@@ -85,7 +94,7 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
        mov     r2, #0
        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
-       orr     r0, r0, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
+       orr     r0, r0, #TTB_FLAGS
        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
        isb
 1:     mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
@@ -115,7 +124,7 @@ ENTRY(cpu_v7_set_pte_ext)
        orr     r3, r3, r2
        orr     r3, r3, #PTE_EXT_AP0 | 2
 
-       tst     r2, #1 << 4
+       tst     r1, #1 << 4
        orrne   r3, r3, #PTE_EXT_TEX(1)
 
        tst     r1, #L_PTE_WRITE
@@ -162,6 +171,11 @@ cpu_v7_name:
  *     - cache type register is implemented
  */
 __v7_setup:
+#ifdef CONFIG_SMP
+       mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
+       orr     r0, r0, #(0x1 << 6)
+       mcr     p15, 0, r0, c1, c0, 1
+#endif
        adr     r12, __v7_setup_stack           @ the local stack
        stmia   r12, {r0-r5, r7, r9, r11, lr}
        bl      v7_flush_dcache_all
@@ -174,14 +188,13 @@ __v7_setup:
 #ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
        mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
-       orr     r4, r4, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
-       mcr     p15, 0, r4, c2, c0, 0           @ load TTB0
+       orr     r4, r4, #TTB_FLAGS
        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
        mov     r10, #0x1f                      @ domains 0, 1 = manager
        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 #endif
-       ldr     r5, =0x40e040e0
-       ldr     r6, =0xff0aa1a8
+       ldr     r5, =0xff0aa1a8
+       ldr     r6, =0x40e040e0
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
        adr     r5, v7_crval
@@ -192,11 +205,11 @@ __v7_setup:
        mov     pc, lr                          @ return to head.S:__ret
 ENDPROC(__v7_setup)
 
-       /*
-        *         V X F   I D LR
-        * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
-        * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
-        *         0 110       0011 1.00 .111 1101 < we want
+       /*   AT
+        *  TFR   EV X F   I D LR
+        * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
+        * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
+        *    1    0 110       0011 1.00 .111 1101 < we want
         */
        .type   v7_crval, #object
 v7_crval: