Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc

[pandora-kernel.git] / arch / arm / mm / proc-v6.S

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index a923aa0..d061d2f 100644 (file)
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -128,20 +128,18 @@ ENTRY(cpu_v6_set_pte_ext)
 
 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
 .globl cpu_v6_suspend_size
-.equ   cpu_v6_suspend_size, 4 * 8
+.equ   cpu_v6_suspend_size, 4 * 6
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v6_do_suspend)
-       stmfd   sp!, {r4 - r11, lr}
+       stmfd   sp!, {r4 - r9, lr}
        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-       mrc     p15, 0, r5, c13, c0, 1  @ Context ID
-       mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
-       mrc     p15, 0, r7, c2, c0, 0   @ Translation table base 0
-       mrc     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-       mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control register
-       mrc     p15, 0, r10, c1, c0, 2  @ co-processor access control
-       mrc     p15, 0, r11, c1, c0, 0  @ control register
-       stmia   r0, {r4 - r11}
-       ldmfd   sp!, {r4- r11, pc}
+       mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+       mrc     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+       mrc     p15, 0, r7, c1, c0, 1   @ auxiliary control register
+       mrc     p15, 0, r8, c1, c0, 2   @ co-processor access control
+       mrc     p15, 0, r9, c1, c0, 0   @ control register
+       stmia   r0, {r4 - r9}
+       ldmfd   sp!, {r4- r9, pc}
 ENDPROC(cpu_v6_do_suspend)
 
 ENTRY(cpu_v6_do_resume)
@@ -150,25 +148,21 @@ ENTRY(cpu_v6_do_resume)
        mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
        mcr     p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
        mcr     p15, 0, ip, c7, c10, 4  @ drain write buffer
-       ldmia   r0, {r4 - r11}
+       mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
+       ldmia   r0, {r4 - r9}
        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-       mcr     p15, 0, r5, c13, c0, 1  @ Context ID
-       mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
-       mcr     p15, 0, r7, c2, c0, 0   @ Translation table base 0
-       mcr     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-       mcr     p15, 0, r9, c1, c0, 1   @ auxiliary control register
-       mcr     p15, 0, r10, c1, c0, 2  @ co-processor access control
+       mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
+       ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
+       ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
+       mcr     p15, 0, r1, c2, c0, 0   @ Translation table base 0
+       mcr     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+       mcr     p15, 0, r7, c1, c0, 1   @ auxiliary control register
+       mcr     p15, 0, r8, c1, c0, 2   @ co-processor access control
        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
        mcr     p15, 0, ip, c7, c5, 4   @ ISB
-       mov     r0, r11                 @ control register
-       mov     r2, r7, lsr #14         @ get TTB0 base
-       mov     r2, r2, lsl #14
-       ldr     r3, cpu_resume_l1_flags
+       mov     r0, r9                  @ control register
        b       cpu_resume_mmu
 ENDPROC(cpu_v6_do_resume)
-cpu_resume_l1_flags:
-       ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
-       ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
 #endif
 
        string  cpu_v6_name, "ARMv6-compatible processor"