Merge branch 'upstream' of git://lost.foo-projects.org/~ahkok/git/netdev-2.6 into...

[pandora-kernel.git] / arch / arm / mm / proc-sa1100.S

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 41f21f2..b23b66a 100644 (file)
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -2,6 +2,7 @@
  *  linux/arch/arm/mm/proc-sa1100.S
  *
  *  Copyright (C) 1997-2002 Russell King
+ *  hacked for non-paged-MM by Hyok S. Choi, 2003.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -26,34 +27,12 @@
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
+#include "proc-macros.S"
+
 /*
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE 32
-#define FLUSH_OFFSET   32768
-
-       .macro flush_1100_dcache rd, ra, re
-       ldr     \rd, =flush_base
-       ldr     \ra, [\rd]
-       eor     \ra, \ra, #FLUSH_OFFSET
-       str     \ra, [\rd]
-       add     \re, \ra, #8192                 @ only necessary for 8k
-1001:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1001b
-#ifdef FLUSH_BASE_MINICACHE
-       add     \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
-       add     \re, \ra, #512                  @ only 512 bytes
-1002:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1002b
-#endif
-       .endm
-
-       .data
-flush_base:
-       .long   FLUSH_BASE
-       .text
 
        __INIT
 
@@ -79,9 +58,8 @@ ENTRY(cpu_sa1100_proc_fin)
        stmfd   sp!, {lr}
        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
        msr     cpsr_c, ip
-       flush_1100_dcache r0, r1, r2            @ clean caches
-       mov     r0, #0
-       mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
+       bl      v4wb_flush_kern_cache_all
+       mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
@@ -102,7 +80,9 @@ ENTRY(cpu_sa1100_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+#ifdef CONFIG_MMU
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+#endif
        mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
@@ -167,14 +147,16 @@ ENTRY(cpu_sa1100_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_sa1100_switch_mm)
-       flush_1100_dcache r3, ip, r1
-       mov     ip, #0
-       mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+#ifdef CONFIG_MMU
+       str     lr, [sp, #-4]!
+       bl      v4wb_flush_kern_cache_all       @ clears IP
        mcr     p15, 0, ip, c9, c0, 0           @ invalidate RB
-       mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+       ldr     pc, [sp], #4
+#else
        mov     pc, lr
+#endif
 
 /*
  * cpu_sa1100_set_pte(ptep, pte)
@@ -183,6 +165,7 @@ ENTRY(cpu_sa1100_switch_mm)
  */
        .align  5
 ENTRY(cpu_sa1100_set_pte)
+#ifdef CONFIG_MMU
        str     r1, [r0], #-2048                @ linux version
 
        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -204,6 +187,7 @@ ENTRY(cpu_sa1100_set_pte)
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+#endif
        mov     pc, lr
 
        __INIT
@@ -213,12 +197,14 @@ __sa1100_setup:
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
+#ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
+#endif
+       adr     r5, sa1100_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, sa1100_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, sa1100_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr
        .size   __sa1100_setup, . - __sa1100_setup
 
@@ -228,12 +214,9 @@ __sa1100_setup:
         * ..11 0001 ..11 1101
         * 
         */
-       .type   sa1100_cr1_clear, #object
-       .type   sa1100_cr1_set, #object
-sa1100_cr1_clear:
-       .word   0x3f3f
-sa1100_cr1_set:
-       .word   0x313d
+       .type   sa1100_crval, #object
+sa1100_crval:
+       crval   clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
 
        __INITDATA
 
@@ -292,6 +275,9 @@ __sa1100_proc_info:
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
        b       __sa1100_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@ -312,6 +298,9 @@ __sa1110_proc_info:
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
        b       __sa1100_setup
        .long   cpu_arch_name
        .long   cpu_elf_name