Pull novell-bugzilla-156426 into release branch

[pandora-kernel.git] / arch / arm / mm / proc-sa110.S

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 34f7e7d..a2dd5ae 100644 (file)
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -18,6 +18,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
@@ -25,22 +26,7 @@
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE 32
-#define FLUSH_OFFSET   32768
 
-       .macro flush_110_dcache rd, ra, re
-       ldr     \rd, =flush_base
-       ldr     \ra, [\rd]
-       eor     \ra, \ra, #FLUSH_OFFSET
-       str     \ra, [\rd]
-       add     \re, \ra, #16384                @ only necessary for 16k
-1001:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1001b
-       .endm
-
-       .data
-flush_base:
-       .long   FLUSH_BASE
        .text
 
 /*
@@ -144,13 +130,11 @@ ENTRY(cpu_sa110_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_sa110_switch_mm)
-       flush_110_dcache        r3, ip, r1
-       mov     r1, #0
-       mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
-       mcr     p15, 0, r1, c7, c10, 4          @ drain WB
+       str     lr, [sp, #-4]!
+       bl      v4wb_flush_kern_cache_all       @ clears IP
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
-       mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
-       mov     pc, lr
+       mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+       ldr     pc, [sp], #4
 
 /*
  * cpu_sa110_set_pte(ptep, pte)
@@ -249,7 +233,7 @@ cpu_sa110_name:
 
        .align
 
-       .section ".proc.info", #alloc, #execinstr
+       .section ".proc.info.init", #alloc, #execinstr
 
        .type   __sa110_proc_info,#object
 __sa110_proc_info: