Merge branch 'clk' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux...
[pandora-kernel.git] / arch / arm / mm / cache-l2x0.c
index db4484f..8ac9e9f 100644 (file)
 #define CACHE_LINE_SIZE                32
 
 static void __iomem *l2x0_base;
-static DEFINE_SPINLOCK(l2x0_lock);
+static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static uint32_t l2x0_way_mask; /* Bitmask of active ways */
 static uint32_t l2x0_size;
 
+struct l2x0_regs l2x0_saved_regs;
+
+struct l2x0_of_data {
+       void (*setup)(const struct device_node *, __u32 *, __u32 *);
+       void (*save)(void);
+       void (*resume)(void);
+};
+
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
        /* wait for cache operation by line or way to complete */
        while (readl_relaxed(reg) & mask)
-               ;
+               cpu_relax();
 }
 
 #ifdef CONFIG_CACHE_PL310
@@ -118,9 +126,9 @@ static void l2x0_cache_sync(void)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void __l2x0_flush_all(void)
@@ -137,9 +145,9 @@ static void l2x0_flush_all(void)
        unsigned long flags;
 
        /* clean all ways */
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        __l2x0_flush_all();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_clean_all(void)
@@ -147,11 +155,11 @@ static void l2x0_clean_all(void)
        unsigned long flags;
 
        /* clean all ways */
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
        cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_inv_all(void)
@@ -159,13 +167,13 @@ static void l2x0_inv_all(void)
        unsigned long flags;
 
        /* invalidate all ways */
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        /* Invalidating when L2 is enabled is a nono */
        BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
        cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_inv_range(unsigned long start, unsigned long end)
@@ -173,7 +181,7 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
        void __iomem *base = l2x0_base;
        unsigned long flags;
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        if (start & (CACHE_LINE_SIZE - 1)) {
                start &= ~(CACHE_LINE_SIZE - 1);
                debug_writel(0x03);
@@ -198,13 +206,13 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
                }
 
                if (blk_end < end) {
-                       spin_unlock_irqrestore(&l2x0_lock, flags);
-                       spin_lock_irqsave(&l2x0_lock, flags);
+                       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                       raw_spin_lock_irqsave(&l2x0_lock, flags);
                }
        }
        cache_wait(base + L2X0_INV_LINE_PA, 1);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_clean_range(unsigned long start, unsigned long end)
@@ -217,7 +225,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
                return;
        }
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
                unsigned long blk_end = start + min(end - start, 4096UL);
@@ -228,13 +236,13 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
                }
 
                if (blk_end < end) {
-                       spin_unlock_irqrestore(&l2x0_lock, flags);
-                       spin_lock_irqsave(&l2x0_lock, flags);
+                       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                       raw_spin_lock_irqsave(&l2x0_lock, flags);
                }
        }
        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_flush_range(unsigned long start, unsigned long end)
@@ -247,7 +255,7 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
                return;
        }
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        start &= ~(CACHE_LINE_SIZE - 1);
        while (start < end) {
                unsigned long blk_end = start + min(end - start, 4096UL);
@@ -260,27 +268,27 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
                debug_writel(0x00);
 
                if (blk_end < end) {
-                       spin_unlock_irqrestore(&l2x0_lock, flags);
-                       spin_lock_irqsave(&l2x0_lock, flags);
+                       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                       raw_spin_lock_irqsave(&l2x0_lock, flags);
                }
        }
        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
        cache_sync();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static void l2x0_disable(void)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&l2x0_lock, flags);
+       raw_spin_lock_irqsave(&l2x0_lock, flags);
        __l2x0_flush_all();
        writel_relaxed(0, l2x0_base + L2X0_CTRL);
        dsb();
-       spin_unlock_irqrestore(&l2x0_lock, flags);
+       raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
-static void __init l2x0_unlock(__u32 cache_id)
+static void l2x0_unlock(__u32 cache_id)
 {
        int lockregs;
        int i;
@@ -356,6 +364,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
                /* l2x0 controller is disabled */
                writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
 
+               l2x0_saved_regs.aux_ctrl = aux;
+
                l2x0_inv_all();
 
                /* enable L2X0 */
@@ -437,7 +447,7 @@ static void __init pl310_of_setup(const struct device_node *np,
 
        of_property_read_u32_array(np, "arm,filter-ranges",
                                   filter, ARRAY_SIZE(filter));
-       if (filter[0] && filter[1]) {
+       if (filter[1]) {
                writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
                               l2x0_base + L2X0_ADDR_FILTER_END);
                writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
@@ -445,33 +455,132 @@ static void __init pl310_of_setup(const struct device_node *np,
        }
 }
 
+static void __init pl310_save(void)
+{
+       u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
+               L2X0_CACHE_ID_RTL_MASK;
+
+       l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
+               L2X0_TAG_LATENCY_CTRL);
+       l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
+               L2X0_DATA_LATENCY_CTRL);
+       l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
+               L2X0_ADDR_FILTER_END);
+       l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
+               L2X0_ADDR_FILTER_START);
+
+       if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+               /*
+                * From r2p0, there is Prefetch offset/control register
+                */
+               l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
+                       L2X0_PREFETCH_CTRL);
+               /*
+                * From r3p0, there is Power control register
+                */
+               if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+                       l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
+                               L2X0_POWER_CTRL);
+       }
+}
+
+static void l2x0_resume(void)
+{
+       if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+               /* restore aux ctrl and enable l2 */
+               l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
+
+               writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
+                       L2X0_AUX_CTRL);
+
+               l2x0_inv_all();
+
+               writel_relaxed(1, l2x0_base + L2X0_CTRL);
+       }
+}
+
+static void pl310_resume(void)
+{
+       u32 l2x0_revision;
+
+       if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+               /* restore pl310 setup */
+               writel_relaxed(l2x0_saved_regs.tag_latency,
+                       l2x0_base + L2X0_TAG_LATENCY_CTRL);
+               writel_relaxed(l2x0_saved_regs.data_latency,
+                       l2x0_base + L2X0_DATA_LATENCY_CTRL);
+               writel_relaxed(l2x0_saved_regs.filter_end,
+                       l2x0_base + L2X0_ADDR_FILTER_END);
+               writel_relaxed(l2x0_saved_regs.filter_start,
+                       l2x0_base + L2X0_ADDR_FILTER_START);
+
+               l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
+                       L2X0_CACHE_ID_RTL_MASK;
+
+               if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+                       writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+                               l2x0_base + L2X0_PREFETCH_CTRL);
+                       if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+                               writel_relaxed(l2x0_saved_regs.pwr_ctrl,
+                                       l2x0_base + L2X0_POWER_CTRL);
+               }
+       }
+
+       l2x0_resume();
+}
+
+static const struct l2x0_of_data pl310_data = {
+       pl310_of_setup,
+       pl310_save,
+       pl310_resume,
+};
+
+static const struct l2x0_of_data l2x0_data = {
+       l2x0_of_setup,
+       NULL,
+       l2x0_resume,
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
-       { .compatible = "arm,pl310-cache", .data = pl310_of_setup },
-       { .compatible = "arm,l220-cache", .data = l2x0_of_setup },
-       { .compatible = "arm,l210-cache", .data = l2x0_of_setup },
+       { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
+       { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
+       { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
        {}
 };
 
 int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask)
 {
        struct device_node *np;
-       void (*l2_setup)(const struct device_node *np,
-               __u32 *aux_val, __u32 *aux_mask);
+       struct l2x0_of_data *data;
+       struct resource res;
 
        np = of_find_matching_node(NULL, l2x0_ids);
        if (!np)
                return -ENODEV;
-       l2x0_base = of_iomap(np, 0);
+
+       if (of_address_to_resource(np, 0, &res))
+               return -ENODEV;
+
+       l2x0_base = ioremap(res.start, resource_size(&res));
        if (!l2x0_base)
                return -ENOMEM;
 
+       l2x0_saved_regs.phy_base = res.start;
+
+       data = of_match_node(l2x0_ids, np)->data;
+
        /* L2 configuration can only be changed if the cache is disabled */
        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
-               l2_setup = of_match_node(l2x0_ids, np)->data;
-               if (l2_setup)
-                       l2_setup(np, &aux_val, &aux_mask);
+               if (data->setup)
+                       data->setup(np, &aux_val, &aux_mask);
        }
+
+       if (data->save)
+               data->save();
+
        l2x0_init(l2x0_base, aux_val, aux_mask);
+
+       outer_cache.resume = data->resume;
        return 0;
 }
 #endif