Merge branch 'stable-3.2' into pandora-3.2

[pandora-kernel.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 67f75a0..ff426dd 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -458,7 +458,6 @@ config CPU_32v5
 config CPU_32v6
        bool
        select TLS_REG_EMUL if !CPU_32v6K && !MMU
-       select CPU_USE_DOMAINS if CPU_V6 && MMU
 
 config CPU_32v6K
        bool
@@ -629,6 +628,24 @@ config IO_36
 
 comment "Processor Features"
 
+config ARM_LPAE
+       bool "Support for the Large Physical Address Extension"
+       depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
+               !CPU_32v4 && !CPU_32v3
+       help
+         Say Y if you have an ARMv7 processor supporting the LPAE page
+         table format and you would like to access memory beyond the
+         4GB limit. The resulting kernel image will not run on
+         processors without the LPA extension.
+
+         If unsure, say N.
+
+config ARCH_PHYS_ADDR_T_64BIT
+       def_bool ARM_LPAE
+
+config ARCH_DMA_ADDR_T_64BIT
+       bool
+
 config ARM_THUMB
        bool "Support Thumb user binaries"
        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
@@ -652,7 +669,7 @@ config ARM_THUMBEE
 
 config SWP_EMULATE
        bool "Emulate SWP/SWPB instructions"
-       depends on !CPU_USE_DOMAINS && CPU_V7
+       depends on CPU_V7
        select HAVE_PROC_CPU if PROC_FS
        default y if SMP
        help
@@ -890,3 +907,18 @@ config ARCH_HAS_BARRIERS
        help
          This option allows the use of custom mandatory barriers
          included via the mach/barriers.h file.
+
+config USER_L2_PLE
+       bool "Enable userspace access to the L2 PLE"
+       depends on CPU_V7
+       default n
+       help
+         Enable userspace access to the L2 preload engine (PLE) available
+         in Cortex-A series ARM processors.
+
+config USER_PMON
+       bool "Enable userspace access to performance counters"
+       depends on CPU_V7
+       default n
+       help
+         Enable userpsace access to the performance monitor registers.